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参数资料
型号： MB9AF311LPMC1
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64
封装： 0.50 MM PITCH, PLASTIC, LQFP-64
文件页数： 25/114页
文件大小： 1357K
代理商： MB9AF311LPMC1
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
18
8.3.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM access is
performed in two clkCPU cycles as described in Figure 8-4.
Figure 8-4. On-chip Data SRAM Access Cycles
8.4
EEPROM Data Memory
The Atmel ATmega48PA/88PA/168PA contains 256/512/512 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase
cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM address
registers, the EEPROM data register, and the EEPROM control register.
Section 28. “Memory Programming” on page 251 contains a detailed description on EEPROM programming in SPI or
parallel programming mode.
8.4.1
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 8-2 on page 22. A self-timing function, however, lets the user
software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some
precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section 8.4.2 “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the
EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the
EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
clk
CPU
T1
Data
RD
WR
Address valid
Compute Address
Next Instruction
Write
Read
Memory Access Instruction
Address
T2
T3
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相关代理商/技术参数
参数描述
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