参数资料
| 型号： | MC100E016FNR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC COUNTER 8BIT SYNC ECL 28-PLCC |
| 产品变化通告： | Reactivation Notice 26/Apr/2011 Product Obsolescence 08/Apr/2011 |
| 标准包装： | 500 |
| 系列： | 100E |
| 逻辑类型： | 二进制计数器 |
| 方向： | 上 |
| 元件数： | 1 |
| 每个元件的位元数： | 8 |
| 复位： | 异步 |
| 计时： | 同步 |
| 计数速率： | 900MHz |
| 触发器类型： | 正边沿 |
| 电源电压： | 4.2 V ~ 5.7 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC（11.51x11.51） |
| 包装： | 带卷 (TR) |
MC10E016, MC100E016
http://onsemi.com
6
Table 9. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = 5.0 V (Note 7)
0°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
151
181
151
181
174
208
mA
VOH
Output HIGH Voltage (Note 8)
1025
950
880
1025
950
880
1025
950
880
mV
VOL
Output LOW Voltage (Note 8)
1810 1705 1620 1810 1745 1620 1810 1740 1620
mV
VIH
Input HIGH Voltage
1165 1025
880
1165 1025
880
1165 1025
880
mV
VIL
Input LOW Voltage
1810 1645 1475 1810 1645 1475 1810 1645 1475
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary 0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC 2.0 V.
Table 10. AC CHARACTERISTICS VCCx= 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = 5.0 V (Note 9)
0°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fMAX
Maximum Toggle Frequency
700
MHz
fCOUNT
Maximum Count Frequency
700
900
700
900
700
900
MHz
tPLH, tPHL Propagation Delay to Output
ps
CLK to Q
500
725
900
500
725
900
500
725
900
MR to Q
500
775
900
500
775
900
500
775
900
CLK to TC
500
775
900
500
775
900
500
775
900
MR to TC
500
775
900
500
775
900
500
775
900
ts
Setup Time (to CLK +)
ps
Pn
150
30
150
30
150
30
CE
600
400
600
400
600
400
PE
600
400
600
400
600
400
TCLD
500
300
500
300
500
300
th
Hold Time (to CLK +)
Pn
350
100
350
100
350
100
CE
400
200
400
200
400
200
PE
0
200
0
200
0
200
TCLD
100
300
100
300
100
300
tRR
Reset Recovery Time
900
700
900
700
900
700
ps
tPW
Minimum Pulse Width
ps
CLK, MR
400
tJITTER
Random Clock Jitter (RMS)
< 1
ps
tr, tf
Rise/Fall Times (20 80%)
200
510
700
200
510
700
200
510
700
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary 0.46 V / +0.06 V.
100 Series: VEE can vary 0.46 V / +0.8 V.
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