参数资料
型号: MC100EL56DWR2G
厂商: ON Semiconductor
文件页数: 1/6页
文件大小: 0K
描述: IC MUX DUAL 2:1 DIFF ECL 20SOIC
标准包装: 1,000
系列: 100EL
类型: 多路复用器
电路: 2 x 2:1
独立电路: 1
电压电源: 双电源
电源电压: 4.2 V ~ 5.7 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC
包装: 带卷 (TR)
Semiconductor Components Industries, LLC, 2008
November, 2008 Rev. 8
1
Publication Order Number:
MC100EL56/D
MC100EL56
5VECL Dual Differential
2:1 Multiplexer
Description
The MC100EL56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or other skew sensitive signals. Multiple VBB pins are
provided to ease AC coupling input signals.
The VBB pins, an internally generated voltage supply, are available
to this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The device features both individual and common select inputs to
address both data path and random logic applications.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open, the D input will pull down to VEE. The D input will bias
around VCC/2 forcing the Q output LOW.
Features
580 ps Typical Propagation Delays
Separate and Common Select
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL
Q Output will Default LOW with Inputs Open or at VEE
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAM*
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
SO20 WB
DW SUFFIX
CASE 751D
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
20
1
100EL56
AWLYYWWG
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