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参数资料
| 型号： | MC100EP222 |
| 厂商： | Motorola, Inc. |
| 英文描述： | Low Voltage ECL/PECL 1:15 Clock Driver(低压ECL/PECL 1:15时钟驱动器) |
| 中文描述： | 低压ECL / PECL的一时15分时钟驱动器（低压ECL / PECL的一时15时钟驱动器） |
| 文件页数： | 1/8页 |
| 文件大小： | 151K |
| 代理商： | MC100EP222 |
SEMICONDUCTOR TECHNICAL DATA
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Motorola, Inc. 2000
06/00
The MC100EP222 is a low voltage, low skew 1:15 differential %1 and %2
ECL/PECL clock distribution buffer. The MC100EP222 has been designed
and optimized for 2.5V and 3.3V systems. Target applications for this clock
driver are high performance clock distribution systems for computer,
networking and telecommunication systems.
Features:
15 differential ECL outputs (4 output banks)
2 selectable differential ECL inputs
Selectable 1:1 or 1:2 frequency outputs
150 ps device-to-device skew
50 ps pin-to-pin skew
Operates from a -2.5, -3.3V (ECL) or 2.5, 3.3V (PECL) power supply
Extended temperature operating range of -40 to +85 deg C
For information on thermal characteristics and its impact on operating life
time refer to AN1545, ”Thermal data for MPC clock drivers”
The MC100EP222 device characteristics allows low-skew clock
distribution of differential and single-ended LVECL/LVPECL signals. Typical
applications for the MC100EP222 are primary clock distribution systems on
backplanes of high-performance computer, networking and
telecommunication systems.
The MC100EP222 can be operated from a 3.3V or 2.5V positive supply (PECL mode) without the requirement of a negative
supply line. Each of the four output banks of two, three, four and six differential clock output pairs may be independently configured
to distribute the input frequency or %2 of the input frequency. The FSELA, FSELB, FSELC, FSELD and CLK_SEL are
asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the the %2 outputs. For
the functionality of the MR control input, “Timing Diagram” on page 2.
Each of the CLK0, CLK1 inputs can be used differential of single-ended. For single-ended signals, connect the bypassed V
BB
output reference to the unused input of the pair.
The MC100EP222 guarantees low output-to-output skew of 50 ps and device-to-device skew of max. 150 ps. To ensure low
skew clock signals in the application, both sides of any differential output pair need to be terminated identically, even if only one
side is used. When fewer than all fifteen pairs are used, identical termination of all output pairs on the same package side is
recommended. If no outputs on a side are used, it is recommended to leave all of these outputs open and unterminated. This will
maintain minimum output skew.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
LOW VOLTAGE 3.3V/2.5V
1:15 DIFFERENTIAL ECL/PECL
CLOCK DRIVER
FA SUFFIX
52–LEAD LQFP PACKAGE
CASE 848D–03
相关PDF资料 |
PDF描述 |
|---|---|
| MC100EP223 | Low-Voltage 1:22 Differential PECL/HSTL Clock Driver(低压1:22差分PECL/HSTL时钟驱动器) |
| MC100H606FN | Registered Hex TTL/PECL Translator |
| MC10H606 | Registered Hex TTL/PECL Translator |
| MC10H606FN | Registered Hex TTL/PECL Translator |
| MC100H607FN | Registered Hex PECL/TTL Translator |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC100EP223 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Low-Voltage 1:22 Differential PECL/HSTL Clock Driver |
| MC100EP223TC | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Low-Voltage 1:22 Differential PECL/HSTL Clock Driver |
| MC100EP24D | 制造商:ON Semiconductor 功能描述: |
| MC100EP29 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset |
| MC100EP29DT | 功能描述:触发器 3.3V/5V ECL Dual RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
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