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参数资料
| 型号： | MC10135L |
| 厂商： | MOTOROLA INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | Replaced by SN54LS175 : Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 |
| 中文描述： | 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 2/5页 |
| 文件大小： | 110K |
| 代理商： | MC10135L |
MC10135
3–23
MOTOROLA
MECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
Pin
Under
Test
Test Limits
–30
°
C
+25
°
C
+85
°
C
Characteristic
Symbol
Min
Max
Min
Typ
Max
Min
Max
Unit
Power Supply Drain Current
IE
IinH
8
75
54
68
75
mAdc
Input Current
6,7,9,10,11
4,5,12,13
425
620
265
390
265
390
μ
Adc
IinL
4,5,6,7,9,
10,11,12,13
0.5
0.5
0.5
0.5
0.3
0.3
μ
Adc
Output Voltage
Logic 1
VOH
2
2 (
3.
)
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage
Logic 0
VOL
3
3 (
3.
)
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
2 (
4.
)
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Threshold Voltage
Logic 0
VOLA
3
3 (
4.
)
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Switching Times (50
Load)
Clock Input
ns
Propagation Delay
t9+2+
t9+2–
t2+, t3+
t2–, t3–
2
2
1.8
1.8
5.0
5.0
1.8
1.8
3.0
3.0
4.5
4.5
1.8
1.8
4.6
4.6
Rise Time
(20 to 80%)
2, 3
1.1
4.8
1.1
2.0
4.5
1.1
4.7
Fall Time
(20 to 80%)
2, 3
1.1
4.8
1.1
2.0
4.5
1.1
4.7
Set Input
ns
Propagation Delay
t5+2+
t12+15+
t5+3–
t12+14–
2
15
3
14
1.8
1.8
1.8
1.8
5.6
5.6
5.6
5.6
1.8
1.8
1.8
1.8
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
1.8
5.2
5.2
5.2
5.2
Reset Input
ns
Propagation Delay
t4+2–
t4+3–
t13+15–
t13+14+
2
3
15
14
1.8
1.8
1.8
1.8
5.6
5.6
5.6
5.6
1.8
1.8
1.8
1.8
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
1.8
1.8
1.8
1.8
5.2
5.2
5.2
5.2
Setup Time
tsetup
7
2.5
2.5
1.0
2.5
ns
Hold Time
thold
7
1.5
1.5
1.0
2.5
ns
Toggle Frequency (Max)
ftog
2
125
125
140
125
MHz
1. Individually test each input; apply VIHmax to pin under test.
2. Individually test each input; apply VILmin to pin under test.
3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax
VILmin
VIHAmax
VILAmin
4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
相关PDF资料 |
PDF描述 |
|---|---|
| MC10135P | Replaced by SN54LS175 : Quadruple D-type Flip-Flops With Clear 16-CFP -55 to 125 |
| MC10136FN | Universal Hexadecimal Counter |
| MC10136 | Universal Hexadecimal Counter |
| MC10136L | 9-Bit Odd/Even Parity Generators/Checkers 14-CDIP -55 to 125 |
| MC10136P | Universal Hexadecimal Counter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC10135P | 制造商:ON Semiconductor 功能描述:Flip Flop JK-Master-Slave Type Pos-Edge 1-Element 16-Pin PDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10136FN | 制造商:ON Semiconductor 功能描述:Counter Single 4-Bit Hexadecimal UP/Down 20-Pin PLLC Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10136FN WAF | 制造商:ON Semiconductor 功能描述: |
| MC10136FNR2 | 制造商:Motorola Inc 功能描述: |
| MC10136L | 制造商:ON Semiconductor 功能描述:Counter Single 4-Bit Hexadecimal UP/Down 16-Pin CDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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