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参数资料
| 型号： | MC10135P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | Replaced by SN54LS175 : Quadruple D-type Flip-Flops With Clear 16-CFP -55 to 125 |
| 中文描述： | 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封装： | PLASTIC, DIP-16 |
| 文件页数： | 3/5页 |
| 文件大小： | 110K |
| 代理商： | MC10135P |
MC10135
MOTOROLA
MECL Data
DL122 — Rev 6
3–24
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
VIHmax
–0.890
VILmin
–1.890
VIHAmin
–1.205
VILAmax
–1.500
VEE
–5.2
–30
°
C
+25
°
C
–0.810
–1.850
–1.105
–1.475
–5.2
+85
°
C
–0.700
–1.825
–1.035
–1.440
–5.2
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(VCC)
Gnd
Characteristic
Symbol
VIHmax
VILmin
VIHAmin
VILAmax
VEE
8
Power Supply Drain Current
IE
IinH
8
1, 16
Input Current
6,7,9,10,11
4,5,12,13
Note 1.
Note 1.
8
8
1, 16
1, 16
IinL
4,5,6,7,9,
10,11,12,13
Note 2.
Note 2.
8
8
1, 16
1, 16
Output Voltage
Logic 1
VOH
2
2 (
3.
)
5
6
8
8
1, 16
1, 16
Output Voltage
Logic 0
VOL
3
3 (
3.
)
5
6
8
8
1, 16
1, 16
Threshold Voltage
Logic 1
VOHA
2
2 (
4.
)
6
5
8
8
1, 16
1, 16
Threshold Voltage
Logic 0
VOLA
3
3 (
4.
)
6
5
8
8
1, 16
1, 16
Switching Times
Clock Input
(50
Load)
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
t9+2+
t9+2–
t2+, t3+
t2–, t3–
2
2
9
9
2
2
8
8
1, 16
1, 16
Rise Time
(20 to 80%)
2, 3
9
2, 3
8
1, 16
Fall Time
(20 to 80%)
2, 3
9
2, 3
8
1, 16
Set Input
Propagation Delay
t5+2+
t12+15+
t5+3–
t12+14–
2
15
3
14
5
12
5
12
2
15
3
14
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Reset Input
Propagation Delay
t4+2–
t4+3–
t13+15–
t13+14+
2
3
15
14
4
4
13
13
2
3
15
14
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Setup Time
tsetup
7
6, 9
2
8
1, 16
Hold Time
thold
7
6, 9
2
8
1, 16
Toggle Frequency (Max)
ftog
2
9
2
8
1, 16
1. Individually test each input; apply VIHmax to pin under test.
2. Individually test each input; apply VILmin to pin under test.
3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax
VILmin
VIHAmax
VILAmin
4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
相关PDF资料 |
PDF描述 |
|---|---|
| MC10136FN | Universal Hexadecimal Counter |
| MC10136 | Universal Hexadecimal Counter |
| MC10136L | 9-Bit Odd/Even Parity Generators/Checkers 14-CDIP -55 to 125 |
| MC10136P | Universal Hexadecimal Counter |
| MC10137L | Replaced by CD54HCT191 : Synchronous Up/Down Counters With Down/Up Mode Control 16-CDIP -55 to 125 |
相关代理商/技术参数 |
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|---|---|
| MC10136FN | 制造商:ON Semiconductor 功能描述:Counter Single 4-Bit Hexadecimal UP/Down 20-Pin PLLC Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10136FN WAF | 制造商:ON Semiconductor 功能描述: |
| MC10136FNR2 | 制造商:Motorola Inc 功能描述: |
| MC10136L | 制造商:ON Semiconductor 功能描述:Counter Single 4-Bit Hexadecimal UP/Down 16-Pin CDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10136P | 制造商:ON Semiconductor 功能描述:Counter Single 4-Bit Hexadecimal UP/Down 16-Pin PDIP Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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