参数资料
型号: MC13110AFB
厂商: MOTOROLA INC
元件分类: 无绳电话/电话
英文描述: UNIVERSAL NARROWBAND FM RECEIVER INTEGRATED CIRCUIT
中文描述: TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP52
封装: PLASTIC, QFP-52
文件页数: 9/68页
文件大小: 1316K
代理商: MC13110AFB
MC13110A/B MC13111A/B
9
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS
(continued)
(VCC = 3.6 V, VB = 1.5 V, TA = 25
°
C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Unit
Max
Typ
Min
Symbol
Measure
Pin
Input
Pin
Figure
LOW BATTERY DETECT
Output Low Voltage (Vin = 1.0 V)
1
Ref1
Ref2
BD1 Out
BD2 Out
VOL
0.2
0.4
V
BATTERY DETECT INTERNAL THRESHOLD
After Electronic Adjustment of VB Voltage
BD Select = (111)
BD Select = (110)
BD Select = (101)
BD Select = (100)
BD Select = (011)
BD Select = (010)
BD Select = (001)
1, 128
VCC Audio
BD2 Out
V
IBS7
IBS6
IBS5
IBS4
IBS3
IBS2
IBS1
3.381
3.298
3.217
3.134
2.970
2.886
2.802
3.455
3.370
3.287
3.202
3.034
2.948
2.862
3.529
3.442
3.357
3.270
3.098
3.010
2.922
PLL PHASE DETECTOR
Output Source Current
(VPD = Gnd + 0.5 V to PLL Vref – 0.5 V)
Rx PD
Tx PD
IOH
1.0
mA
Output Sink Current
(VPD = Gnd + 0.5 V to PLL Vref – 0.5 V)
Rx PD
Tx PD
IOL
1.0
mA
PLL LOOP CHARACTERISTICS
Maximum 2nd LO Frequency
(No Crystal)
LO2 In
f2ext
12
MHz
Maximum 2nd LO Frequency
(With Crystal)
LO2 In
LO2 Out
f2ext
12
MHz
Maximum Tx VCO (Input Frequency),
Vin = 200 mVpp
Tx VCO
ftxmax
80
MHz
PLL VOLTAGE REGULATOR
Regulated Output Level (IL = 0 mA, after Vref
Adjustment)
1
PLL Vref
VO
2.4
2.5
2.6
V
Line Regulation (IL = 0 mA, VCC = 3.0 to 5.5 V)
Load Regulation (IL = 1.0 mA)
1
VCC Audio
VCC Audio
PLL Vref
PLL Vref
VReg Line
VReg
Load
11.8
40
mV
1
–20
–1.4
mV
MICROPROCESSOR SERIAL INTERFACE
Input Current Low (Vin = 0.3 V, Standby Mode)
1
Data,
Clk, EN
IIL
–5.0
0.4
μ
A
Input Current High (Vin = 3.3 V, Standby Mode)
1
Data,
Clk, EN
IIH
1.6
5.0
μ
A
Hysteresis Voltage
Data,
Clk, EN
Vhys
1.0
V
Maximum Clock Frequency
Data,
EN, Clk
2.0
MHz
Input Capacitance
Data,
Clk, EN
Cin
8.0
pF
EN to Clk Setup Time
106
EN, Clk
tsuEC
tsuDC
th
trec
tw
tpuMPU
200
ns
Data to Clk Setup Time
105
Data, Clk
100
ns
Hold Time
105
Data, Clk
90
ns
Recovery Time
106
EN, Clk
90
ns
Input Pulse Width
EN, Clk
100
ns
MPU Interface Power–Up Delay (90% of PLL Vref
to Data,Clk, EN)
108
100
μ
s
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