MC1321x Serial Peripheral Interface (SPI)
MC1321x Reference Manual, Rev. 1.6
4-20
Freescale Semiconductor
c) The first word (or 2 bytes) read during a Packet RAM read should be discarded as the internal
Packet RAM address is not accessed for the first word read operation. This has the effect of
adding 2 bytes to the byte count.
3. Do a recursive SPI read transaction where:
a) MCU asserts CE low.
b) MCU sends the MC1321x the first SPI burst with header field of R/W bit = 1 and address field
Addr[5:0] = 0x01 for the RX_Pkt_RAM register address.
c) MCU reads MC1321x data with the number of SPI byte bursts as calculated in Number 2
above. Note that the first two bytes read from the MC1321x are discarded and that the number
of SPI read bursts must be an even number. For an odd number of bytes, the one byte is also
discarded, and the odd byte is read from the lower 8 bits of the register.
d) MCU negates CE high.
4.11.3.1.2
Receive Packet RAM Read Access Error Conditions
Two types of errors can occur during a Packet RAM read:
1. RAM address error - if the recursive read access exceeds 64 words (128 SPI data bursts), the
internal read address counter will exceed the RAM address and generate an error indication via
status bit ram_addr_err, IRQ_Status Register 24, Bit 14. An interrupt request can be generated with
the error status by setting mask bit ram_addr_mask, IRQ_Mask Register 5, Bit 12. As with other
interrupt requests, the status is cleared by reading the IRQ_Status register.
2. RAM arbitration busy - if the transceiver internal logic attempts to access the RAM during a SPI
read access (a SPI read during an active Rx sequence), an error indication will be generated via
status bit arb_busy_err, IRQ_Status Register 24, Bit 13. An interrupt request can be generated with
the error status by setting mask bit arb_busy_mask, IRQ_Mask Register 5, Bit 11. As with other
interrupt requests, the status is cleared by reading the IRQ_Status register.
4.11.3.2
Recursive Transmit Packet RAM Write Access
The transmit Packet RAM is normally accessed when the MC1321x is in Packet Data Mode and a frame
is to be transmitted. The number of transmit data bytes in the transmit queue is loaded into the
tx_pkt_length[6:0] field (this represents the full payload which includes the data bytes stored in the
transmit Packet RAM plus the 2 CRC bytes).
The data is written to the TX_Pkt_RAM Register 02 with a recursive access. When accessing
TX_Pkt_RAM Register 02, the SPI register address pointer is NOT incremented, instead, the Packet RAM
write address pointer is incremented. Therefore, by using a recursive write, up to 64 words of packet
memory can be written via the SPI with an access that requires but a single header field. A write access to
Packet RAM always starts at the bottom of the RAM, i.e., the write address pointer always starts at the
beginning of the data for a given write.