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参数资料
| 型号： | MC13783JVK5 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 26/50页 |
| 文件大小： | 0K |
| 描述： | IC PWR MGT AUD CIRCUIT 247MAPBGA |
| 标准包装： | 240 |
| 应用： | 手持/移动设备 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 247-TFBGA |
| 供应商设备封装： | 247-MAPBGA（10x10） |
| 包装： | 托盘 |
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Functional Description
4.3
4.3.1
4.3.1.1
Audio
Dual Digital Audio Bus
Interface
The MC13783 is equipped with two independent digital audio busses. Both busses consist of a bit clock,
word clock, receive data and transmit data signal lines. Both busses can be redirected to either the voice
CODEC or the stereo DAC and can be operated simultaneously. In addition to the afore mentioned signal
lines, two system clock inputs are provided which can be selected to drive the voice CODEC or the stereo
DAC. In the latter case, a PLL is used to generate the proper internal frequencies. During simultaneous use
of the both busses, two different system clocks can be selected by the voice CODEC and the stereo DAC.
4.3.1.2
Voice CODEC protocol
The serial interface protocol for the voice CODEC can be used in master and in slave mode. In both modes,
it can operate with a short or a long frame sync and data is transmitted and received in a two's compliment
format.
CDCFS[1:0]=01
Short Frame Sync
Length = Bit
FS
FSync
BitCLK
CDCFS[1:0]=10
Long Frame Sync
Length = 16 Bit
CDCFSINV=0
CDCBCLINV=0
TX
TX
HIGH Z
15 14 13 12 11 10
9
8
7
6
5
4
3
0
0 0
HIGH Z
RX
Don't
Care
15 14 13 12 11 10
9
8
7
6
5
4
3
0
0
0
Don't
Care
Figure 6. Voice Codec Timing Diagram Example 1
When the voice CODEC is in slave mode, the FS input must remain synchronous to the CLI frequency. In
master mode all clocks are internally generated based on the CLI signal.
Additional programmability of the interface for both master and slave mode include bus protocol selection
and FS and BCL inversion. There is also the possibility to activate the clocking circuitry independent from
the voice CODEC.
4.3.1.3
Stereo DAC protocol
The serial interface protocol for the stereo DAC supports the industry standard MSB justified mode and an
I2S mode. In industry standard mode, FS will be held high for one 16-bit data word and low for the next
16 bits. I2S mode is similar to industry standard mode except that the serial data is delayed one BCL
period. Data is received in a two's compliment format. A network mode is also available where the stereo
MC13783 Technical Data, Rev. 3.5
26
Freescale Semiconductor
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相关代理商/技术参数 |
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|---|---|
| MC13783JVK5R2 | 功能描述:接口—CODEC ATLAS 3G PWRMNGMNT 5 RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| MC13783VK | 功能描述:IC PWR MNGMNT ATLAS 3G 247MAPBGA RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
| MC13783VK5 | 功能描述:电池充电器 ATLAS 3G PWRMNGMNT 5 RoHS:否 制造商:Power-Sonic 化学性质:Sealed Lead Acid 输出电压:12 V 输出电流:500 mA 端接类型:Screw |
| MC13783VK5R2 | 功能描述:电池充电器 ATLAS 3G PWRMNGMNT 5 RoHS:否 制造商:Power-Sonic 化学性质:Sealed Lead Acid 输出电压:12 V 输出电流:500 mA 端接类型:Screw |
| MC13783VKR2 | 功能描述:IC PWR MNGMNT ATLAS 3G 247MAPBGA RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
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