参数资料
型号: MC13783VK5R2
厂商: Freescale Semiconductor
文件页数: 20/50页
文件大小: 0K
描述: IC PWR MNGMNT ATLAS 3G 247MAPBGA
标准包装: 1
应用: 手持/移动设备
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 247-TFBGA
供应商设备封装: 247-MAPBGA(10x10)
包装: 标准包装
其它名称: MC13783VK5R2DKR
Functional Description
CS
T clkper
T selsu
T clkhigh
T clklow
T selhld
T sellow
CLK
MOSI
T wrtsu
T wrthld
T rden
T rdsu
T rdhld
T rddis
MISO
Figure 4. SPI Interface Timing Diagram
Table 6. SPI Interface Timing Specifications
Parameter
T selsu
T selhld
T sellow
T clkper
T clkhigh
T clklow
T wrtsu
T wrthld
T rdsu
T rdhld
T rden
T rddis
Description
Time CS has to be high before the first rising edge of CLK
Time CS has to remain high after the last falling edge of CLK
Time CS has to remain low between two transfers
Clock period of CLK 1
Part of the clock period where CLK has to remain high
Part of the clock period where CLK has to remain low
Time MOSI has to be stable before the next rising edge of CLK
Time MOSI has to remain stable after the rising edge of CLK
Time MISO will be stable before the next rising edge of CLK
Time MISO will remain stable after the falling edge of CLK
Time MISO needs to become active after the rising edge of CS
Time MISO needs to become inactive after the falling edge of CS
T min (ns)
20
20
20
50
20
20
5
5
5
5
5
5
1
Equivalent to a maximum clock frequency of 20 MHz.
Table 7. SPI Interface Logic IO Specifications
Parameter
Input High CS, MOSI, CLK
Input Low CS, MOSI, CLK
Output Low MISO, INT
Output High MISO, INT
Condition
Output sink 100 μ A
Output source 100 μ A
Min
0.7*VCC
0
0
VCC-0.2
Max
VCC+0.5
0.3*VCC
0.2
VCC
Units
V
V
V
V
20
Note:
VCC refers to PRIVCC and SECVCC respectively.
MC13783 Technical Data, Rev. 3.5
Freescale Semiconductor
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