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参数资料
| 型号： | MC13892AJVLR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 106/158页 |
| 文件大小： | 0K |
| 描述： | IC PMU I.MX51/37/35/27 186MAPBGA |
| 标准包装： | 1,000 |
| 应用： | 电池管理，显示器（LED 驱动器），手持/移动设备，电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 186-LFBGA |
| 供应商设备封装： | 186-PBGA（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
ADC SUBSYSTEM
8 Bit Address Header
24 B it Data
Location
43
Location
44
Location
45
Location
46
Location
47
ADC Control
Register 0
ADC Control
Register 1
ADC Result
Register ADC0
ADC Control
Register 2
ADC Result
Register ADC1
R/W
Bi t
R/W
Bi t
R/W
Bi t
R/W
Bi t
R/W
Bi t
Address
Bits
Address
Bits
Address
Bits
Address
Bits
Address
Bits
Nul l ADC
Bi t BIS0
Nul l ADC
Bi t BIS1
Nul l
Bi t
Nul l ADC
Bi t BIS2
Nul l
Bi t
ADC Control
Bits
ADC Control
Bits
ADC Result
Bits
ADC Control
Bits
ADC BIS Result
Bits
Figure 28. ADC Register Set for ADC BIS Access
There are two interrupts available to inform the processor when the ADC has finished its conversions, one for the standard
ADC conversion ADCDONEI, and one for the ADCBIS conversion ADCBISDONEI. These interrupts will go high after the
conversion, and can be masked.
When two requests are queued, the request for which the trigger event occurs the first will be converted the first. During the
conversion of the first request, an ADTRIG trigger event of the other request is ignored, if for the other request the TRIGMASK
bit was set to 1. When this bit is set to 0, the other request ADTRIG trigger event is memorized, and the conversion will take place
directly after the conversions of the first request are finished.
The following diagram shows the influence of the TRIGMASK bit. The TRIGMASK bit is particularly of use when an ADC
conversion has to be lined up to a periodically ADTRIG initiated conversion. In case of ASC initiated conversions, the TRIGMASK
bit is of no influence.
Figure 29. TRIGMASK Functional Diagram
To avoid results of previous conversions getting overwritten by a periodical ADTRIG signal, a single shot function is enabled
by setting the ADONESHOT bit to a one. In that case, only at the first following conversion, an ADTRIG trigger event is accepted.
ASC events are not affected by this setting. Before performing a new single shot conversion, the ADONESHOT bit first needs to
be cleared. Note that this bit is available for each of the conversion requests 'ADC' or 'ADC BIS', so can be set independently.
It is possible to queue two ADTRIG triggered conversions. Both conversions will be executed with a priority based on the
TRIGMASK setting. If both conversion requests have identical TRIGMASK settings, priority is given to the 'ADC' conversion over
the 'ADC BIS' conversion. Note that the ADONESHOT is also taken into account.
To avoid that the ADTRIG input inadvertently triggers a conversion, the ADTRIGIGN bit can be set which will ignore any
transition on the ADTRIG pin. The ADC completely ignores either ADTRIG or ASC pulses while ADEN is low. When reading
conversion results, it is preferable to make ADEN = 0.
MC13892
Analog Integrated Circuit Device Data
106
Freescale Semiconductor
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相关代理商/技术参数 |
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| MC13892BJVK | 功能描述:PMIC 解决方案 PMUIC W/4 BUCK/12 LDO RG RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC13892BJVKR2 | 功能描述:PMIC 解决方案 PMUIC W/4 BUCK/12 LDO RG RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC13892BJVL | 功能描述:PMIC 解决方案 PMUIC W/4 BUCK/12 LDO RG RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC13892BJVLR2 | 功能描述:PMIC 解决方案 PMUIC W/4 BUCK/12 LDO RG RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC13892CJVK | 功能描述:PMIC 解决方案 POWER MGMT IC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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