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参数资料
| 型号： | MC14027BFL1 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 锁存器 |
| 英文描述： | 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封装： | EIAJ, PLASTIC, SOIC-16 |
| 文件页数： | 5/10页 |
| 文件大小： | 205K |
| 代理商： | MC14027BFL1 |
MC14027B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ (8.)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns
tTLH,
tTHL
5.0
10
15
—
100
50
40
200
100
80
ns
Propagation Delay Times**
Clock to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
tPLH,
tPHL
5.0
10
15
—
175
75
50
350
150
100
ns
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
5.0
10
15
—
175
75
50
350
150
100
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns
5.0
10
15
—
350
100
75
450
200
150
Setup Times
tsu
5.0
10
15
140
50
35
70
25
17
—
ns
Hold Times
th
5.0
10
15
140
50
35
70
25
17
—
ns
Clock Pulse Width
tWH, tWL
5.0
10
15
330
110
75
165
55
38
—
ns
Clock Pulse Frequency
fcl
5.0
10
15
—
3.0
9.0
13
1.5
4.5
6.5
MHz
Clock Pulse Rise and Fall Time
tTLH, tTHL
5.0
10
15
—
—
15
5.0
4.0
s
Removal Times
Set
trem
5
10
15
90
45
35
10
5
3
—
ns
Reset
5
10
15
50
25
20
– 30
– 15
– 10
—
Set and Reset Pulse Width
tWH
5.0
10
15
250
100
70
125
50
35
—
ns
7. The formulas given are for the typical characteristics only at 25
_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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