MOTOROLA CMOS LOGIC DATA
MC14029B
122
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
All Types
Unit
Characteristic
Symbol
VDD
Min
Typ #
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clk to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Cin to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 95 ns
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
PE to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
PE to Cout
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL
5.0
10
15
—
200
100
90
400
200
180
ns
Clk to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Cin to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 95 ns
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
PE to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
PE to Cout
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL
5.0
10
15
—
250
130
85
500
260
190
ns
out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Cin to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 95 ns
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
PE to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
PE to Cout
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL
5.0
10
15
—
175
50
360
120
100
ns
out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Cin to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 95 ns
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
PE to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
PE to Cout
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL
5.0
10
15
—
235
100
80
470
200
160
ns
out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Cin to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 95 ns
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
PE to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
PE to Cout
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL
5.0
10
15
—
320
145
105
640
290
210
ns
Clock Pulse Width
tW(cl)
5.0
10
15
180
80
60
90
40
30
—
ns
Clock Pulse Frequency
fcl
5.0
10
15
—
4.0
8.0
10
2.0
4.0
5.0
MHz
Preset Removal Time
The Preset Signal must be low prior to a positive–going
transition of the clock.
trem
5.0
10
15
160
80
60
80
40
30
—
ns
Clock Rise and Fall Time
tr(cl)
tf(cl)
5.0
10
1 5
—
—
15
5
4
s
Carry In Setup Time
tsu
5.0
10
15
150
60
40
75
30
20
—
ns
Up/Down Setup Time
5.0
10
15
340
140
100
170
70
50
—
ns
Binary/Decade Setup Time
5.0
10
15
320
140
100
160
70
50
—
ns
Preset Enable Pulse Width
tW
5.0
10
15
130
70
50
65
35
25
—
ns
* The formulas given are for the typical characteristics only at 25
_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.