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参数资料
| 型号： | MC14069UBFL2 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 门电路 |
| 英文描述： | 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| 封装： | EIAJ, PLASTIC, SOIC-14 |
| 文件页数： | 1/10页 |
| 文件大小： | 123K |
| 代理商： | MC14069UBFL2 |
Semiconductor Components Industries, LLC, 2000
August, 2000 – Rev. 4
1
Publication Order Number:
MC14069UB/D
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin–for–Pin Replacement for CD4069UB
Meets JEDEC UB Specifications
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
–0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
–0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
–55 to +125
°C
Tstg
Storage Temperature Range
–65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14069UBCP
PDIP–14
2000/Box
MC14069UBD
SOIC–14
2750/Box
MC14069UBDR2
SOIC–14
2500/Tape & Reel
MC14069UBDT
TSSOP–14
MC14069UBF
SOEIAJ–14
96/Rail
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP–14
P SUFFIX
CASE 646
MC14069UBCP
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
1
14
14069U
AWLYWW
14
069U
ALYW
1
14
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14069U
ALYW
MC14069UBFEL
SOEIAJ–14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14069UBDTR2 TSSOP–14 2500/Tape & Reel
MC14069UBDTEL TSSOP–14 2000/Tape & Reel
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