MC144111DWR2 (Freescale) PDF资料下载 Datasheet(11/12 页)

您现在的位置：买卖IC网 > PDF目录2012 > MC144111DWR2 (Freescale Semiconductor)IC QUAD SERIAL D/A CONV 16-SOIC PDF资料下载

参数资料

MC144110 Technical Data, Rev. 2

Freescale Semiconductor

Pin Descriptions

4.1

INPUTS

Din

Data Input

Six-bit words are entered serially, MSB first, into digital data input, Din. Six words are loaded into the

MC144110 during each D/A cycle; four words are loaded into the MC144111.

The last 6-bit word shifted in determines the output level of pins Q1 Out and R1 Out. The next-to-last 6-bit

word affects pins Q2 Out and R2 Out, etc.

ENB

Negative Logic Enable

The ENB pin must be low (active) during the serial load. On the low-to-high transition of ENB, data

contained in the shift register is loaded into the latch.

CLK

Shift Register Clock

Data is shifted into the register on the high-to-low transition of CLK. CLK is fed into the D-input of a

transparent latch, which is used for inhibiting the clocking of the shift register when ENB is high.

The number of clock cycles required for the MC144110 is usually 36. The MC144111 usually uses 24

cycles. See Table 4 for additional information.

4.2

OUTPUTS

Dout

Data Output

The digital data output is primarily used for cascading the DACs and may be fed into Din of the next stage.

R1 Out through Rn Out

Resistor Network Outputs

These are the R-2R resistor network outputs. These outputs may be fed to high-impedance input FET op

amps to bypass the on-chip bipolar transistors. The R value of the resistor network ranges from 7 to 15 k

发布紧急采购，3分钟左右您将得到回复。

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购