参数资料
型号: MC145152DW2
厂商: Freescale Semiconductor
文件页数: 10/24页
文件大小: 0K
描述: IC PAR-IN PLL FREQ SYNTH 28-SOIC
标准包装: 26
类型: PLL 时钟/频率合成器
PLL:
输入: 时钟
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 无/无
频率 - 最大: 25MHz
除法器/乘法器: 是/无
电源电压: 3 V ~ 9 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 管件
MC145151-2 and MC145152-2 Technical Data, Rev. 5
18
Freescale Semiconductor
Design Considerations
4
Design Considerations
4.1
Phase-Locked Loop — Low-Pass Filter Design
Figure 12. Phase-Locked Loop — Low-Pass Filter Design
C)
_
+
A
C
R2
C
VCO
C
VCO
R2
B)
A)
C
VCO
PDout
φ
R -
φ
V -
PDout -
φ
R
φ
V
R1
R2
NOTE: Sometimes R1 is split into two series resistors, each R1 ÷ 2. A capacitor CC is then placed from the midpoint to ground to further
filter
φ
V and φR. The value of CC should be such that the corner frequency of this network does not significantly affect ωn.
The
φ
R and φV outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
Definitions:
N = Total Division Ratio in feedback loop
Kφ (Phase Detector Gain) = VDD/4π for PDout
Kφ (Phase Detector Gain) = VDD/2π for φV and φR
KVCO (VCO Gain) =
2
πf
VCO
V
VCO
for a typical design wn (Natural Frequency)
2
πfr
10
(at phase detector input).
Damping Factor:
ζ 1
φ
R -
φ
V -
F(s) =
Assuming gain A is very large, then:
F(s) =
ζ =
ω
n =
NR1C
R1sC + 1
ω
n =
ζ =
ω
nR2C
2
R2sC + 1
R1sC
1
N
ω
n
2KφKVCO
F(s) =
ζ =
ω
n =
(R1+R2)sC+1
R2sC+1
NC(R1 + R2)
R2C+
N
KφKVCO
NCR1
0.5
ω
n
KφKVCO
(
)
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