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参数资料
| 型号： | MC14557BFL1 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 计数移位寄存器 |
| 英文描述： | 4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16 |
| 封装： | EIAJ, PLASTIC, SOIC-16 |
| 文件页数： | 5/10页 |
| 文件大小： | 202K |
| 代理商： | MC14557BFL1 |
MC14557B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ (8.)
Max
Unit
Rise and Fall Time, Q or Q Output
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5
10
15
—
100
50
40
200
100
80
ns
Propagation Delay, Clock or CE to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
tPLH,
tPHL
5
10
15
—
300
130
90
600
260
180
ns
Propagation Delay, Reset to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 70 ns
tPLH,
tPHL
5
10
15
—
300
130
95
600
260
190
ns
Pulse Width, Clock
tWH(cl)
5
10
15
200
100
75
95
45
35
—
ns
Pulse Width, Reset
tWH(rst)
5
10
15
300
140
100
150
70
50
—
ns
Clock Frequency (50% Duty Cycle)
fcl
5
10
15
—
3.0
7.5
13.0
1.7
5.0
6.7
MHz
Setup Time, A or B to Clock or CE
Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = VSS (Register Length = 1)
tsu
5
10
15
700
290
145
350
130
85
—
ns
Best case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
10
15
400
165
60
45
5
0
—
Hold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = VSS (Register Length = 1)
th
5
10
15
200
100
10
– 150
– 60
– 50
—
ns
Worst case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
10
15
400
185
85
50
25
22
—
Rise and Fall Time, Clock
tr,
tf
5
10
15
No Limit
—
Rise and Fall Time, Reset or CE
tr,
tf
5
10
15
—
15
5
4
s
Removal Time, Reset to Clock or CE
trem
5
10
15
160
80
70
80
40
35
—
ns
7. The formulas given are for the typical characteristics only at 25
_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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