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参数资料
| 型号： | MC16V1CPU20B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 16/128页 |
| 文件大小： | 571K |
| 代理商： | MC16V1CPU20B1 |
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MOTOROLA
MC68HC16V1
112
MC68HC16V1TS/D
SCSR contains flags that show SCI operational conditions. These flags can be cleared either by hard-
ware or by a special acknowledgment sequence. The sequence consists of SCSR read with flags set,
followed by SCDR read (write in the case of TDRE and TC). A long-word read can consecutively access
both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read,
but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits,
but before the CPU has written or read register SCDR, the newly set status bit is not cleared. SCSR
must be read again with the bit set. Also, SCDR must be written or read before the status bit is cleared.
Reading either byte of SCSR causes all 16 bits to be accessed. Any status bit already set in either byte
will be cleared on a subsequent read or write of register SCDR.
TDRE — Transmit Data Register Empty Flag
0 = Register TDR still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to the transmit data register.
TDRE is set when the byte in the transmit data register is transferred to the transmit serial shifter. If
TDRE is zero, transfer has not occurred and a write to the transmit data register will overwrite the pre-
vious value. New data is not transmitted if the transmit data register is written without first clearing
TDRE.
TC — Transmit Complete Flag
0 = SCI transmitter is busy
1 = SCI transmitter is idle
TC is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or
queued breaks (logic zero). The interrupt can be cleared by reading SCSR when TC is set and then by
writing the transmit data register of SCDR.
RDRF — Receive Data Register Full Flag
0 = Receive data register is empty or contains previously read data.
1 = Receive data register contains new data.
RDRF is set when the content of the receive serial shifter is transferred to the receive data register. If
one or more errors are detected in the received word, flag(s) NF, FE, and/or PF are set within the same
clock cycle.
RAF — Receiver Active Flag
0 = SCI receiver is idle
1 = SCI receiver is busy
RAF indicates whether the SCI receiver is busy. It is set when the receiver detects a possible start bit
and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in
systems with multiple masters.
IDLE — Idle-Line Detected Flag
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
IDLE is disabled when RWU in SCCR1 is set. IDLE is set when the SCI receiver detects the idle-line
condition specified by ILT in SCCR1. If cleared, IDLE will not set again until after RDRF is set. RDRF
is set when a break is received, so that a subsequent idle line can be detected.
OR — Overrun Error Flag
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
OR is set when a new byte is ready to be transferred from the receive serial shifter to the receive data
register, and RDRF is still set. Data transfer is inhibited until OR is cleared. Previous data in receive
data register remains valid, but data received during overrun condition (including the byte that set OR)
is lost.
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