参数资料
| 型号： | MC33143DW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 5/8页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH DUAL H-SIDE 24-SOIC |
| 标准包装： | 30 |
| 类型： | 高端 |
| 输入类型： | 非反相 |
| 输出数： | 2 |
| 导通状态电阻： | 140 毫欧 |
| 电流 - 峰值输出： | 6A |
| 电源电压： | 9 V ~ 17 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 管件 |
MC33143
Freescale Semiconductor, Inc.
Figure 2. Output Response Waveform
5.0 V
IN1–2
0V
tdlh
50%
tdhl
VPwr
OUT1–2
0V
VPwr – 3.0 V
2.0 V
tSRr
PIN FUNCTION DESCRIPTION
tSRf
Pin
1, 12
2
3, 10
4, 9, 16,
21
5, 6, 7, 8,
17, 18,
19, 20
11
13, 24
Symbol
IN1, IN2
CEN
STAT1. STAT2
VPwr
Gnd
VDD
OUT1, OUT2
Description
INput 1 and INput 2 (IN1 and IN2) respectively determine the state of the corresponding output drivers
(OUT1 and OUT2) under normal operating conditions. When an input is high, it’s corresponding output
is active ON, and when low is disabled OFF. IN1 and IN2 have internal active pull–downs which allow a
floating input pin to be conservatively interpreted as a logic low, turning Off the output. An unused input
should be connected to ground.
Chip Enable (CEN) input pin, when low, disables both outputs (OUT1 and OUT2) and places the device
in a “sleep mode” reducing the bias current required from VDD and VPwr. A falling edge of CEN causes
OUT1 and OUT2 to rapidly turn OFF. A falling edge of CEN should precede any VDD shutdown to allow
time OUT1 and OUT2 to be disabled. When CEN is low, INTerrupt (INT) and STATus 1 and 2 (STAT1–2)
will be tri–stated (high impedance). The CEN pin can also be used for power–on reset and under
voltage lockout to disable the outputs for power supply voltages less than 4.5 V. CEN is a dependent
input from the system microcontroller unit (MCU) or some other integrated circuit. It has an internal
pull–up resistor to VDD affording a floating pin to be interpreted as a logic high. Rpull–up is greater than
50 k ? . If used externally, this pin should be connected to VDD.
The STATus pins (STAT1–2) respectively indicate the presence of faults on OUT1–2. STAT1–2 will be
logic high during normal operation. A logic low will occur whenever an Open Load, Short–to–Ground,
Short–to–Supply (Battery), Thermal Limit, or Overvoltage Shutdown fault condition is experienced on a
corresponding output. STAT1–2 are both active low digital drivers. A 10 k ? resistor between STAT1–2
and the system CPU may improve a Failure Mode Evaluation Analysis (FMEA) score if STAT1–2 are
externally shorted to VPwr. If unused, this pin should be left connected.
These pins are connected to the supply and provide load current to the DMOS outputs, are used
pumping the DMOS gates, and for Overvoltage shutdown detection of the DMOS. The DMOS outputs
will turn ON with 5.5 to 24 V applied to VPwr. VPwr is limited to –1.5 V for a maximum duration of
250 ms. A 10 nF de–coupling cap is recommended to be used from VPwr to Ground.
These eight pins constitute the circuits ground (Gnd) and also provide heatsinking for the DMOS output
transistors. Ground continuity is required for the outputs2 to turn ON.
This pin is to be connected to the 5.0 V logic supply of the system. A 10 nF de–coupling capacitor is
recommended from VDD to Gnd.
These pins are connected internally to the DMOS output transistors which source current into the
corresponding load. Each output incorporates dynamic clamping to accommodate inductive loads. In
addition, each output has independent short to ground detection and protection, current limit detection
and protection, thermal limit detection and protection, ON open load and or short to supply (battery)
detection. Neither output will turn ON if CEN is logic low. An unused output should be connected to a
10 k ? load to prevent false fault reporting. A 1.0 nF filter capacitor may be used from OUT to Gnd to
provide dV/dt noise filtering.
MOTOROLA ANALOG IC DEVICE For More Information On This Product,
DATA
Go to: www.freescale.com
5
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