参数资料
| 型号： | MC33143DW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH DUAL H-SIDE 24-SOIC |
| 标准包装： | 30 |
| 类型： | 高端 |
| 输入类型： | 非反相 |
| 输出数： | 2 |
| 导通状态电阻： | 140 毫欧 |
| 电流 - 峰值输出： | 6A |
| 电源电压： | 9 V ~ 17 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 管件 |
MC33143
Freescale Semiconductor, Inc.
PIN FUNCTION DESCRIPTION (continued)
Pin
14
15
23
Symbol
SFPD
GTST
INT
Description
This is a Short Fault Protect Disable (SFPD) input; which when logic high disables the internal current
limit timer preventing OUT1–2 from latching OFF when confronted with an overcurrent condition. The
condition of SFPD does not affect fault reporting. Current and thermal limit remain active when the
SFPD pin is logic high. Having the SFPD pin logic high facilitates the device to drive incandescent lamp
loads with peak in–rush currents in excess of three amperes. When SFPD is logic low, an overcurrent
demand will latch OFF only the output affected. The device will then automatically begin active
re–enabling of the corresponding output affected for the duration of the overcurrent condition. SFPD has
an internal active pull–down which affords a floating input pin condition to be conservatively interpreted
as a logic low. A 10 k ? resistor between SFPD and the system CPU may improve the FMEA score if
SFPD is externally shorted to OUT2. SFPD should be connected to Gnd or VDD for the desired
operating mode and not be left “floating”.
The Gate TeST (GTST) pin is used to stress the devices DMOS gates during testing operations. This pin
should normally be connected to ground in the application.
The INTerrupt pin INT is active logic low and indicates the presence of a fault on either the output. INT
can be paralleled with additional fault pins and use d as a system CPU interrupt to indicate the presence
of a fault. The system CPU can then read STAT1–2 to determine the specific type of fault occurring. INT
will be l ogi c high during normal operation. A logic low will result if a fault occurs on either OUT1 or
OUT2. INT has an internal active pull–up and requires no external pull–up resistor to be used. The INT
output has sufficient current drive capability to afford paralleling of u p t o five INT pins. A 10 k ? resistor
between INT and the system CPU may improve the FMEA score if INT is externally shorted to OUT1.
This pin should be left unconnected if the feature is not used.
Figure 3. Function Table
Device Condition
Normal
Output to Gnd Short
In
Low
High
Low
High
Out
Low
High
Low
High/Low
STAT
High
High
High
Low
Output Condition
Normal OFF
Normal ON
Normal OFF
Output in active retry mode.
STAT Condition
Normal
Normal
Normal
Short fault reported. Fault
Normal ON when short is
removed.
clears when short is removed.
Open Load
Low
High
Low
Normal OFF
“OFF” open fault reported. Fault
clears when load is connected.
High
High
Low
Normal ON
“ON” open fault reported. Fault
clears when load is connected.
Output to VPwr
Short
Low
HIgh
High
High
Low
Low
Normal OFF
Normal ON
“OFF” open fault reported. Fault
clears when short is removed.
“ON” open fault reported. Fault
clears when short is removed.
Over Temperature
Low
Low
Low
Normal OFF
Thermal fault reported. Fault
clears with no thermal limit.
High
Low
Low
Output disabled. Output Retries
Thermal fault reported. IN low
with no thermal limit.
and no thermal limit required to
clear the fault.
VPwr Overvoltage
Low
Low
Low
Normal OFF
Overvoltage fault reported.
Fault clears with no
overvoltage.
High
Low
Low
Output disabled. Will reset with
Overvoltage fault reported.
no overvoltage.
Fault clears with no
overvoltage.
“Sleep”/Under
Low
Low
High–Z
Output disabled.
STAT tri–stated, no faults
Voltage Mode,
reported.
CEN Low
High
Low
High–Z
Output disabled.
STAT tri–stated, no faults
reported.
For More Information On This Product,
6
MOTOROLA ANALOG IC DEVICE DATA
Go to: www.freescale.com
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