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参数资料
| 型号： | MC33291L |
| 厂商： | 飞思卡尔半导体(中国)有限公司 |
| 英文描述： | Eight Output Switch with Serial Peripheral Interface I/O(带SPI接口的八输出开关) |
| 中文描述： | 8个串行外围接口的I / O（带的SPI接口的八输出开关输出开关） |
| 文件页数： | 15/24页 |
| 文件大小： | 633K |
| 代理商： | MC33291L |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33291L
15
register is full after eight bits of information have been entered.
To preserve data integrity, care should be taken to not transition
SI as SCLK transitions from a low-to-high logic state.
SO Pin
The serial output (SO) pin is the
tri-stateable
output from the
Shift register. The SO pin remains in a high impedance state
until the CS pin goes to a logic low state. The SO data reports
the drain status, either high or low relative to the previous
command word. The SO pin changes state on the rising edge
of SCLK and reads out on the falling edge of SCLK. When an
output is OFF and not faulted, the corresponding SO data-bit is
a high state. When an output is ON, and there is no fault, the
corresponding data-bit on the SO pin will be a low logic state.
The SI/SO shifting of data follows a first-in-first-out (FIFO)
protocol with both input and output words transferring the MSB
first. Referring to Figure 16, the DO
bit is the MSB
corresponding to Output 7 relative to the previous command
word. The SO pin is not affected by the status of the Reset pin.
RST Pin
The 33291L reset (RST) pin is active low. It is used to clear
the SPI Shift register. In doing so, all output switches are set at
OFF. The device situated in the same system with an MCU, the
MCU retains the Reset pin of the device in a logic low state.
Retention ensures all outputs to be OFF until both the V
DD
and
V
PWR
pin voltages are adequate for predictable operation.
Retention of the device Reset pin takes place only upon initial
system power up. After the 33291L is reset, the MCU is ready
to assert system control with all output switches initially OFF.
If the V
PWR
pin of the 33291L experiences a low voltage,
following normal operation, the MCU should pull the Reset pin
low to shutdown the outputs and clear the input data register.
The Reset pin is active low and has an internal pull-down
incorporated, insuring operational predictability should the
external pull-down of the MCU open circuit. The internal pull-
down is only 25 μA, affording safe and easy interfacing to the
MCU. The Reset pin of the 33291L should be pulled to a logic
low state for a duration of at least 250 ns, ensuring reliable a
reset.
Figure 15. Power ON Reset
A simple power ON reset delay of the system can be
programmed through the use of an RC network comprised of a
shunt capacitor from the Reset pin to Ground and a resistor to
V
DD
, illustrated in Figure 15. Care should be exercised ensuring
proper discharge of the capacitor. Careful attention eliminates
adverse delay of the Reset and damage of the MCU if it pulls
the Reset line low, thereby accomplishing initialization for turn
ON delay. It may be easier to incorporate delay into the
software program and use a parallel port pin of the MCU to
control the 33291L Reset pin.
SFPD Pin
The Short Fault Protect Disable (SFPD) pin is used to
prevent the outputs from latching-off due to an over current
condition. This feature provides control of incandescent lamp
loads where in-rush currents exceed the device’s analog
current limits. Essentially the SFPD pin determines whether the
33291L output(s) will instantly shutdown upon sensing an
output short or remain ON in a current limiting mode of
operation until the output short is removed or thermal shutdown
is reached. If the SFPD pin is tied to V
DD
= 5.0 V the 33291L
output(s) will remain ON in a current limited mode of operation
upon encountering a load short to supply or over current
condition. When the SFPD pin is grounded, a short circuit will
immediately shut down only the output affected. Other outputs
not having a fault condition will operate normally. The short
circuit operation is addressed in more detail later.
Power Consumption
The 33291L has extremely low power consumption in both
the operating and standby modes. In the standby, or
Sleep
mode, with V
DD
≤
2.0 V, the current consumed by the V
PWR
pin
is less than 25 μA. In the operating mode, the current drawn by
the V
DD
pin is less than 4.0 mA (1.0 mA typical) while the
current drawn at the V
PWR
pin is 2.0 mA maximum (1.0 mA
typical). During normal operation, turning outputs ON increases
I
PWR
by only 20 μA per output. Each output experiencing a
soft
short
(over current conditions just under the current limit), adds
0.5 mA to the I
PWR
current.
Paralleling of Outputs
Using MOSFETs as output switches permits connecting any
combination of outputs together. R
DS(on)
of MOSFETs have an
inherent positive temperature coefficient providing balanced
current sharing between outputs without destructive operation
(bipolar outputs could not be paralleled in this fashion as
thermal run-away would likely occur). The device can even be
operated with all outputs tied together. This mode of operation
may be desirable in the event the application requires lower
power dissipation, or the added capability of switching higher
currents.
Performance of parallel operation results in a corresponding
decrease in R
DS(on)
while the Output OFF Open Load Detect
Currents and the Output Current Limits increase
correspondingly (by a factor of eight if all outputs are
paralleled). Less than 125 m
R
DS(on)
at 25
°
C with current
limiting of eight to 24 A will result if all outputs are paralleled
together. There will be no change in the over voltage detect or
+
V
DD
R
DLY
C
DLY
Reset
20 μA
Reset
MCU
33291LL
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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