参数资料
型号: MC33291L
厂商: 飞思卡尔半导体(中国)有限公司
英文描述: Eight Output Switch with Serial Peripheral Interface I/O(带SPI接口的八输出开关)
中文描述: 8个串行外围接口的I / O(带的SPI接口的八输出开关输出开关)
文件页数: 9/24页
文件大小: 633K
代理商: MC33291L
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33291L
9
.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V
V
DD
5.5 V, 9.0 V
V
PWR
16 V, -40
°
C
T
A
125
°
C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Interface Timing
Required Low State Duration for Reset (VIL < 0.2 VDD) (Note 31)
t
W(RST)
50
167
ns
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
t
LEAD
50
167
ns
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
t
LAG
50
167
ns
SI to Falling Edge of SCLK (Required for Setup Time)
t
SI(SU)
25
83
ns
Falling Edge of SCLK to SI (Required for Hold Time)
t
SI(HOLD)
25
83
ns
SO Rise Time (CL = 200 pF)
t
R(SO)
25
50
ns
SO Fall Time (CL = 200 pF)
t
F(SO)
25
50
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 32)
t
R(SI)
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 32)
t
F(SI)
50
ns
Time from Falling Edge of CS to SO Low Impedance (Note 33)
t
SO(EN)
110
ns
Time from Rising Edge of CS to SO High Impedance (Note 34)
t
SO(DIS)
110
ns
Time from Rising Edge of SCLK to SO Data Valid (Note 35)
0.2 VDD < SO > 0.8 VDD, CL = 200 pF
t
VALID
65
105
ns
Notes:
31.
32.
33.
34.
35.
RST Low duration measured with outputs enabled and going to OFF or disabled condition.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at the SO pin.
Time required for output status data to be terminated at the SO pin.
Time required to obtain valid data out from SO following the rise of SCLK. See (Note 4).
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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