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| 型号： | MC33389DDWR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 33/49页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM BASE W/CAN 28-SOIC |
| 标准包装： | 1 |
| 控制器类型： | 系统基础芯片 |
| 接口： | CAN |
| 电源电压： | 5.5 V ~ 18 V |
| 电流 - 电源： | 45mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 剪切带 (CT) |
| 其它名称： | MC33389DDWR2CT |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
39
33389
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
.
This register reports the CANL and Tx permanent failure status
This register monitors the status of the V2, V3, and VBAT voltage level.
Table 36. TESRH Bit Definition
TESRH3
TESRH2
TESRH1
TESRH0
Description
0
No Failure on CANH
0
x
0
1
CANH Wire Interruption
x
1
x
CANH Short Circuit to VBAT
0
1
0
x
CANH Short Circuit to Ground
1
x
0
x
CANH Short Circuit to VCC
In case of CANH line failures, the appropriate bit(s) are set according to Table 36. This information is latched. The register can be reset by a
Read operation. After power-ON is reset, all bits are set to 0.
Table 37. Transceiver Error Status Register for CANL and Tx (TESRL)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TESRL
$017
R
TESRL3
TESRL2
TESRL1
TESRL0
W
RESET
—
0
Table 38. TESRL Bit Definition
TESRL3
TESRL2
TESRL1
TESRL0
Description
0
No Failure
0
x
0
1
CANL Wire Interruption
0
1
0
x
CANL Short Circuit to Ground/CANH mutually shorted to CANL
x
1
x
CANL Short Circuit to VBAT
1
x
0
x
CANL Short Circuit to VDD
In case of CANL line failures, the appropriate bit(s) are set according to Table 38. This information is latched. The register can be reset by a
Read operation. After power-ON is reset, all bits are set to 0.
Table 39. Reset Source Register (RSR)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RSR
$018
R
RSR2
RSR1
RSR0
W
RESET
—
1
0
1
This register reports the source of a reset already occurred.
RSR0: 1 = > VDD1 under voltage occurred (RSR2 = 1 in this case), 0 = > no over voltage on V occurred
RSR1: 1 = > Software watchdog reset occurred (RSR 2 = 1 in this case), 0 = > no SW watchdog reset occurred
RSR2: 1 = > External reset occurred (RSR0 = RSR1= 0 in this case), 0 = > no external reset occurred
Events related to the bits in register RSR are latched. All bits can be reset by a Read operation of the register. After a power-ON reset, RSR2
and RSR0 are set to 1. Therefore, the first read out of the register after power-ON delivers RSR[2:0] = [101].
Table 40. Voltage Supply Status Register (VSSR)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VSSR
$01B
R
V3SR
V2SR
VBSR1
VBSR0
W
RESET
—
0
—
POR
—
0
1
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