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参数资料
| 型号： | MC33701 |
| 厂商： | 飞思卡尔半导体(中国)有限公司 |
| 英文描述： | 1.5 A Switch-Mode Power Supply with Linear Regulator(1.5 A开关方式电源，带线性稳压器) |
| 中文描述： | 1.5开关模式电源，线性稳压器（1.5 A的开关方式电源，带线性稳压器） |
| 文件页数： | 14/24页 |
| 文件大小： | 841K |
| 代理商： | MC33701 |
33701
14
Go to: www.freescale.com
the boost regulator output capacitor reaches its regulation limit,
the low-side switch is turned off until the output voltage falls
below the regulation limit again.
Oscillator
A 300 kHz (default) oscillator sets the switching frequency of
the buck regulator. The frequency of the oscillator can be
adjusted between 200 kHz and 400 kHz by an optional external
resistor R
F
connected from the FREQ pin of the integrated
circuit to ground. See
Figure 4
for frequency resistor selection.
The CLKSYN pin can be configured either as an oscillator
output when the CLKSEL pin is left open or it can be used as a
synchronization input when the CLKSEL pin is grounded. The
oscillator output signal is a square wave logic signal with
50 percent duty cycle, 180 degrees out-of-phase with the
internal clock signal. This allows opposite phase
synchronization of two 3370x devices.
When the CLKSYN pin is used as synchronization input
(CLKSEL pin grounded), the external resistor R
F
chosen from
the chart in
Figure 4
should be used to synchronize the internal
slope compensation ramp to the external clock. Operation is
only recommended between 200 kHz and 400 kHz. The
supplied synchronization signal does not need to be 50 percent
duty cycle. Minimum pulse width is 300 ns.
Low Dropout Linear Regulator (LDO)
The adjustable low dropout linear regulator (LDO) is capable
of supplying a 1.0 A output current. It has a current limit with
retry capability. When the voltage measured across the current
sense resistor reaches the 45 mV threshold, the control circuit
limits the current for 1.0 ms and if the overcurrent condition still
exists the linear regulator is turned off. At the same time the
overcurrent condition is detected, the Retry Timer starts to time
out. When the timer expires after 100 ms, the LDO tries to
power up again for 1.0 ms, repeatedly checking for the
overcurrent condition. The current limit of the LDO can be set
by using the following formula:
I
LIM
= 45 mV/R
S
Where R
S
is the LDO current sense resistor, connected
between the CS pin and the LDO pin output (see
Figure 20
).
When no current sense resistor is used, it is still possible to
detect the overcurrent condition by tying the current sense pin
CS to the V
BST
voltage. In this case, the overcurrent condition
is sensed by saturation of the linear regulator driver buffer.
The output voltage of the LDO can be adjusted by means of
an external resistor divider connected to the feedback control
pin LFB. The linear regulator output voltage can be adjusted in
the range of 0.8 V to 5.0 V, but the LDO output voltage is always
lower than the input voltage to the regulator. Power-up, power-
down, and fault management are coordinated with the
switching regulator.
Thermal Shutdown
The LDO pull-down FET Q4 has an independent thermal
shutdown control. When the Q4 temperature exceeds the
thermal shutdown limit, the Q4 will be turned off without
affecting the LDO operation.
Voltage Margining
The 33701 includes a voltage margining feature accessed
through the I
2
C bus. Voltage margining allows for independent
adjustment of the Switcher V
OUT
voltage and the linear output
V
LDO
. Each can be adjusted up and down in 1% steps to a
range of ±7%. This feature allows for worst case system
validation; i.e., determining the design margin. Margining
details are described in the section entitled
I
2
C Bus Operation
,
beginning on page 19 of this datasheet.
RESET
The
RESET
pin is an open drain output. The Reset Control
circuit supervises both output voltages—the linear regulator
output V
LDO
and the switching regulator output V
OUT
. When
either of these two regulators is out of regulation (high or low),
the
RESET
pin is pulled low. There is a 20
μ
s delay filter
preventing erroneous resets. During power-up sequencing,
RESET
is held low until the Reset Timer times out.
Reset Timer Power-Up Delay (RT)
The Reset Timer Power-Up Delay (RT) pin is used to set the
delay between the time when the LDO and switcher outputs are
active and stable and the release of the
RESET
output. An
external resistor and capacitor are used to program the timer.
The power-up delay can be obtained by using the following
formula:
T
D
= 10 ms + R
t
C
t
Where R
t
is the Reset Timer programming resistor and C
t
is the
Reset Timer programming capacitor, both connected in parallel
from RT to ground.
Note
Observe the maximum C
t
value and expect reduced
accuracy if R
t
is less than 10 k
.
Watchdog Timer
A watchdog function is available via I
2
C bus communication.
It is possible to select either window watchdog or time-out
watchdog operation, as illustrated in
Figure 9
on page 15.
Watchdog time-out starts when the watchdog function is
activated via I
2
C bus sending a Watchdog Programming
command byte, thus determining watchdog operation (window
or time-out) and period duration (refer to
Table 1
, page 15). If
the watchdog is cleared by receiving a new Watchdog
Programming command through the I
2
C bus, the watchdog
timer is reset and the new time-out period begins. If the
watchdog time expires, the
RESET
will become active (LOW)
for a time determined by the RC components of the RT timer
plus 10 ms. After a watchdog time-out, the function is no longer
active.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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