参数资料
型号: MC33742
厂商: 飞思卡尔半导体(中国)有限公司
元件分类: CAN
英文描述: System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver(带增强型高速CAN收发器的系统基片)
中文描述: 系统基础芯片的增强型(SBC)的高速CAN收发器(带增强型高速的CAN收发器的系统基片)
文件页数: 3/52页
文件大小: 1087K
代理商: MC33742
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33742
3
TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section beginning on
page 18
.
Terminal
Terminal
Name
Formal Name
Definition
1
RXD
Receive Data
CAN bus receive data output
2
TXD
Transmit Data
CAN bus transmit data input
3
V
DD
Voltage Digital Drain
5.0 V regulator output terminal.
4
RST
Reset Output
(Active LOW)
This is the device reset output whose main function is to reset the MCU. This terminal
has an internal pull-up current source to V
DD
5
INT
Interrupt Output
(Active LOW)
This output is asserted LOW when an enabled interrupt condition occurs. The output
is a push-pull structure.
6–9
20–23
GND
Ground
Ground of the IC. These terminals are connected to the package lead frame in order to
provide a thermal path.
10
V2
Voltage Source 2
Sense input for V2 regulator using external ballast. V2 is also the internal supply for the
CAN cell.
11
V2CTRL
Voltage Source 2 Control
Output driver for the external ballast transistor.
12
V
SUP
Voltage Supply
Supply input for the complete device.
13
HS
High-Side Output
Output of internal high-side switch. Current capability is internally limited to 150 mA.
14–17
L0–L3
Level 0–3 Inputs
Input interfaces to external circuitry (switched or ICs). Levels at these terminals can be
read by SPI and input can be used as programmable wake-up input in Sleep or Stop
mode.
18
CANH
CAN High
CAN high output.
19
CANL
CAN Low
CAN low output.
24
SCLK
Serial Data Clock
Clock input for the Serial Peripheral Interface (SPI) of the device.
25
MISO
Master In/Slave Out
SPI data sent to MCU. When
CS
is HIGH, terminal is high impedance.
26
MOSI
Master Out/Slave In
SPI data received by the 33742.
27
CS
Chip Select
(Active LOW)
Chip select terminal for SPI. When
CS
is LOW, device is selected.
28
WDOG
Watchdog Output
(Active LOW)
Output of watchdog circuitry. Terminal is asserted LOW if software watchdog is not
correctly triggered.
WDOG
CS
MOSI
MISO
SCLK
GND
GND
GND
GND
CANL
CANH
L3
L2
L1
RXD
TXD
V
DD
RST
INT
GND
GND
GND
GND
V2
V2CTRL
V
SUP
HS
L0
4
5
6
7
8
9
10
11
12
13
14
2
3
28
25
24
23
22
21
20
19
18
17
16
15
27
26
1
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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