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| 型号： | MC33780EGR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 9/37页 |
| 文件大小： | 0K |
| 描述： | IC DBUS MASTER DUAL DIFF 16-SOIC |
| 标准包装： | 1,000 |
| 系列： | * |
| 类型： | * |
| 应用： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
17
33780
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
SPREAD SPECTRUM
Figure 12. Spread Spectrum Block Diagram
The dominant source of radiated electromagnetic
interference (EMI) from the DBUS bus is due to the regular
periodic frequency of the data bits. At a steady bit rate, the
time period for each bit is the same, which results in a steady
fundamental frequency plus harmonics. This results in
undesired signals appearing at multiples of the frequency
that can be strong enough to interfere with a desired signal.
A significant decrease of radiated EMI can be achieved by
randomly changing the duration of each bit. This can
significantly reduce the amplitude by having the signal spend
a much smaller percentage of time at any specific frequency.
The signal strength of the fundamental and harmonics are
reduced directly by the percentage of time it spends on a
specific frequency. For instance, if the bit rate is 136 kbps,
there will be a harmonic at 680 kHz. If it is changed in
frequency so that only 1/10 of the bits are at the 136 kbps
rate, the signal energy at 680 kHz will be reduced by 90%.
A circuit to do this is included in this IC and can perform the
spreading of the signal independently for each channel. This
is done in the Spread Spectrum (SS) Block Diagram shown
in Figure 12.
Spreading can be enabled by setting the SSENn bits in the
DnSSCTRL registers. There are 64 possible bit durations that
are equally spaced between the shortest and longest bit
times. Because they are evenly spaced by a time difference
and not by a frequency difference (the reciprocal of time), all
frequency domain parameters of the SS block are expressed
in units of time.
VCO
The output of the voltage-controlled oscillator (VCO) is
used as the bit rate clock. Three cycles of this clock are used
to create each bit of data on the DBUS.
There are two voltages that control the period (1/
frequency) of the signal coming from the VCO. The voltage
coming from the Center Frequency DAC (Digital-to-Analog
Converter) in Figure 12 is used to keep the average period
constant. The voltage coming from the Spreader DAC
changes the period in random steps to spread the signal. The
Phase Locked Loop (PLL)-derived changes are much slower
to update the period than the ones derived from the Spreader
Logic. This prevents the two “loops” from interacting with
each other.
PLL
The PLL loop compensates for temperature drift and the
variations in processing of the IC that would otherwise
change the average data rate (center frequency). It does this
by comparing a time reference derived from the clock signal
(4.0 MHz) to the period of the VCO output. If the ratio is not
correct, it will change the frequency of the VCO by changing
the digital value it sends to the Center Frequency DAC.
The PLL has fast and slow update rates for making these
changes. It enters a fast update mode automatically anytime
the OFFSET register is written to using the SPI, or following
a reset. This fast acquisition mode consists of 64 VCO update
cycles (1.4 ms per update cycle) that last about 90 ms. This
is done to quickly adjust the center frequency after changes
have been made. After the fast acquisition, the PLL switches
PLL Logic
Spreader Logic
Center
Frequency
DAC
Modulation
DAC
VCO
CLK (4.0 MHz typ)
CLK_VCOn (408 kHz typ)
OFFSET[8:0]
PLLOFF
SSEN
DEV[1:0]
PRBS[1:0]
SSUD
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