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| 型号： | MC33790DW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 13/13页 |
| 文件大小： | 0K |
| 描述： | IC DSI 2-CHAN INTERFACE 16-SOIC |
| 标准包装： | 47 |
| 类型： | 分布式系统接口 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | SPI |
| 电流 - 电源： | 1mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
33790
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33790 is designed to provide the interface between logic
and the DSI bus. It accepts signals with a typical 0 V to 5.0 V
logic level to control the state of the bus output (Idle Level,
Logic High Level, Logic Low Level, and High Impedance). It
detects the current drawn from the bus output during
signaling and outputs a 0 V to 5.0 V logic level corresponding
to the bus current being above (Logic [1] out) the bus return
logic [1] current or below (Logic [0] out). The 33790 contains
current limiting of the bus outputs as required by the DSI Bus
specification and thermal shutdown to protect itself from
damage. Two independent DSI bus outputs are provided by
the IC.
FUNCTIONAL TERMINAL DESCRIPTION
Bus Driver and Receiver
The Wave-Shaper converts the 0 to 5.0 V logic inputs from
DSIxF (frame) and DSIxS (signal) to a wave-shaped signal
on the DSIxO output, as shown in the timing diagrams in
Current Sense detects the current being drawn by the
device(s) on the bus during signalling (DSIxF=0). If the
current is above a set level, DSIxR will be high; otherwise, it
is low. Due to the variations in the turnaround time (tTAT) from
slave devices and bus delays, DSIxR should be sampled on
the falling edge of DSIxS and on the rising edge of DSIxF (for
the last return bit).
The current for the idle state is from the supply connected to
VSUP and this supply should not be current limited below
250 mA per channel. During idle state, the voltage on the DSI
bus will be very close to the VSUP voltage.
Internal thermal shutdown circuitry and current limit
individually protect the DSIxO outputs from shorts to battery
and ground.
Typically, the thermal shutdown occurs between 160 °C and
170 °C. If the junction temperature rises above this
temperature, the internal TxLIM bit is asserted, and the output
drivers for DSIxO are disabled by the thermal shutdown
circuitry. The output drivers remain off until the junction
temperature decreases below approximately 155 °C, at
which time the thermal shutdown circuitry turns off and the
outputs are re-enabled. Each DSIxO output has a unique
thermal sense and shutdown circuit, so a short on one
channel does not affect the other channel.
Charge Pump
The charge pump uses on-board capacitors to step the input
voltage up to the voltage needed to drive the on-board
transmitter FETs. A filter/storage capacitor is connected to
CPCAP to hold the stepped-up voltage.
Input Pull-ups and Pull-downs
Internal current pull-ups are used on the DSIxF pins and
pulldowns on the DSIxS pins. If these pins are left
unconnected, their associated DSI bus will go to the unused
(high-impedance) state.
Table 6. DSI Bus Truth Table
DSIxF
DSIxS
TxLIM
DSIxR
DSIxO
0
Not Defined
Low (1.5 V)
0
1
0
Not Defined
High (4.5 V)
0
0
Return Data
Unchanged
X
0
Return Data
Unchanged
1
0
High Impedance
1
0
Idle
V
SUP - 0.5 V
X
1
High Impedance
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