参数资料
型号: MC33880
厂商: 飞思卡尔半导体(中国)有限公司
英文描述: Configurable Octal Serial Switch with Serial Peripheral Interface I/O(可配置的8串行开关,带串行外围I/O口(SPI))
中文描述: 配置八路系列开关串行外设接口输入/输出(可配置的8串行开关,带串行外围的I / O口(SPI)的)
文件页数: 11/24页
文件大小: 741K
代理商: MC33880
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880
11
DIGITAL INTERFACE TIMING
Recommended Frequency of SPI Operation
4.0
6.0
MHz
Required Low State Duration on V
DD
for Reset (Note 16)
V
DD
0.2 V
t
RESET
4.0
10
μ
s
Falling Edge of
CS
to Rising Edge of SCLK (Required Setup Time)
t
LEAD
100
ns
Falling Edge of SCLK to Rising Edge of
CS
(Required Setup Time)
t
LAG
50
ns
DI to Falling Edge of SCLK (Required Setup Time)
t
DI(su)
16
ns
Falling Edge of SCLK to DI (Required Hold Time)
t
DI(HOLD)
20
ns
DI,
CS
, SCLK Signal Rise Time (Note 17)
t
R(DI)
5.0
ns
DI,
CS
, SCLK Signal Fall Time (Note 17)
t
F(DI)
5.0
ns
Time from Falling Edge of
CS
to DO Low Impedance (Note 18)
t
DO(EN)
60
ns
Time from Rising Edge of
CS
to DO High Impedance (Note 19)
t
DO(DIS)
60
ns
Time from Rising Edge of SCLK to DO Data Valid (Note 20)
t
VALID
25
60
ns
Notes
16.
17.
18.
19.
20.
This parameter is guaranteed by design but is not production tested.
Rise and Fall time of incoming DI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at DO pin.
Time required for output status data to be terminated at DO pin
Time required to obtain valid data out from DO following the rise of SCLK.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions of 4.75 V
V
DD
5.25 V, 9.0 V
V
PWR
16 V, -40
°
C
T
C
125
°
C unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with V
PWR
= 13 V, T
A
= 25
°
C.
Characteristic
Symbol
Min
Typ
Max
Units
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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