参数资料
型号: MC33880
厂商: 飞思卡尔半导体(中国)有限公司
英文描述: Configurable Octal Serial Switch with Serial Peripheral Interface I/O(可配置的8串行开关,带串行外围I/O口(SPI))
中文描述: 配置八路系列开关串行外设接口输入/输出(可配置的8串行开关,带串行外围的I / O口(SPI)的)
文件页数: 18/24页
文件大小: 741K
代理商: MC33880
33880
18
Go to: www.freescale.com
FUNCTIONAL PIN DESCRIPTION
CS Pin
The system MCU selects the 33880 to communicate through
the use of the
CS
pin. Whenever the pin is in a logic low state,
data can be transferred from the MCU to the 33880 device and
vice versa. Clocked-in data from the MCU is transferred from
the 33880 shift register and latched into the power outputs on
the rising edge of the
CS
signal. On the falling edge of the
CS
signal, output status information is transferred from the power
outputs status register into the device's shift register. The falling
edge of
CS
enables the DO output driver. Whenever the
CS
pin
goes to a logic low state, the DO pin output is enabled, thereby
allowing information to be transferred from the 33880 to the
MCU. To avoid any spurious data, it is essential the high-to-low
transition of the
CS
signal occurs only when SCLK is in a logic
low state.
SCLK Pin
The system clock pin (SCLK) clocks the internal shift
registers of the 33880. The serial data input (DI) is latched into
the input shift register on the falling edge of the SCLK. The
serial data output pin (DO) shifts data out of the shift register on
the rising edge of the SCLK signal. False clocking of the shift
register must be avoided to guarantee validity of data. It is
essential the SCLK pin be in a logic low state whenever chip
select pin (
CS
) makes any transition. For this reason, it is
recommended the SCLK pin is commanded to a logic low state
when the device is not accessed (
CS
in logic high state). When
the
CS
is in a logic high state, any signal at the SCLK and DI pin
is ignored and the DO is tri-stated (high impedance).
DI Pin
This pin is used for serial instruction data input. DI
information is latched into the input register on the falling edge
of SCLK. A logic high state present on DI will program a specific
output on. The specific output will turn on with the rising edge of
the
CS
signal. Conversely, a logic low state present on the DI
pin will program the output
off
. The specific output will turn
off
with the rising edge of the
CS
signal. To program the eight
outputs of the 33880 device
on
or
off
, enter the DI pin beginning
with Output 8, followed by Output 7, Output 6, and so on to
Output 1. For each falling edge of the SCLK while
CS
is logic
low, a data bit instruction (
on
or
off)
is loaded into the shift
register per the data bit DI state. Eight bits of entered
information fills the shift register. To preserve data integrity, do
not transition DI as SCLK transitions from a high to low logic
state.
DO Pin
The serial data output (DO) pin is the output from the shift
register. The DO pin remains tri-state until the
CS
pin goes to a
logic low state. All faults on the 33880 device are reported as
logic [1] through the DO data pin. Regardless of the
configuration of the driver, open loads and shorted loads are
reported as logic [1]. Conversely, normal operating outputs with
non-faulted loads are reported as logic [0]. The first positive
transition of SCLK will make output eight status available on DO
pin. Each successive positive clock will make the next output
status available. The DI/DO shifting of data follows a first-in-
first-out protocol with both input and output words transferring
the most significant bit (MSB) first.
EN Pin
The EN pin on the 33880 device either enables or disables
the internal charge pump. The EN pin must be high for this
device to enhance the gates of the output drivers, perform fault
detection, and reporting. Active outputs during a low transition
of the EN pin will become active again when the EN transitions
high. If this feature is not required, it is recommended the EN
pin be connected to V
DD
.
IN5 and IN6 Pins
The IN5 and IN6 pins command inputs allowing outputs five
and six to be used in PWM applications. IN5 and IN6 pins are
ORed with the SPI communication input. For SPI control of
outputs five and six, the IN5 and IN6 pins should be grounded
or held low by the microprocessor. In the same manner, when
using the PWM feature the SPI port must command the outputs
off
. Maximum PWM frequency for each output is 2.0 kHz.
V
DD
Pin
The V
DD
pin supplies logic power to the 33880 device and is
used for power-on reset (POR). To achieve low standby current
on V
PWR
supply, power must be removed from the V
DD
pin. The
device will be in reset with all drivers off when V
DD
is below
3.9 V
DC
.
D1–D8 Pins
The D1–D8 pins are the open drain outputs of the 33880. For
High-Side Drive configurations, the drain pins are connected to
battery supply. In Low-Side Drive configurations, the drain pins
are connected to the low side of the load. All outputs may be
configured individually as desired. When Low-Side Drive is
used, the 33880 limits the positive transient for inductive loads
to 45 V.
S1–S8 Pins
The S1–S8 pins are the source outputs of the 33880. For
High-Side Drive configurations, the source pins are connected
directly to the load. In Low-Side Drive configurations the source
is connected to ground. All outputs may be configured
individually as desired. When High-Side drive is used, the
33880 will limit the negative transient for inductive loads to
-20 V.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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