参数资料
型号: MC33882
厂商: 飞思卡尔半导体(中国)有限公司
英文描述: Six-Output Low-Side Switch with SPI and Parallel Input Control(带SPI和并口输入控制的6输出低端开关)
中文描述: 六输出低压侧开关SPI和并行输入控制(带的SPI和并口输入控制的6输出低端开关)
文件页数: 3/24页
文件大小: 779K
代理商: MC33882
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33882
3
HSOP TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
Definition
1
V
PWR
Load Supply Voltage
This terminal is connected to battery voltage. A decoupling cap is required from V
PWR
to ground.
2
19
28
IN0 & IN1
IN2 & IN3
IN4 & IN5
Input 0 & Input 1
Input 2 & Input 3
Input 4 & Input 5
These input terminals control two output channels each when the
MODE
terminal is
pulled high. These terminals may be connected to pulse width modulated (PWM)
outputs of the control IC while the
MODE
terminal is high. The states of these terminals
are ignored during normal operation (
MODE
terminal low) and override the normal
inputs (serial or parallel) when the
MODE
terminal is high. These terminals have
internal active 25
μ
A pull-downs.
3
MODE
Mode Select
The
MODE
terminal is connected to the
MODE
terminal of the control IC. This terminal
has an internal active 25
μ
A pull-up.
4
6
9
18
21
24
27
29
IN0
IN1
IN2
IN7
IN3
IN4
IN5
IN6
Input 0–Input7
These are parallel control input terminals. These terminals have internal 25
μ
A active
pull-downs.
5
7
10
17
20
23
26
30
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
OUT6
Output 0–Output7
Each terminal is one channel's drain, sinking current for the respective load.
8, 11, 22, 25
NC
No Connect
Not connected.
12
SI
Serial Input
The Serial Input terminal is connected to the SPI Serial Data Output terminal of the
control IC from where it receives output command data. This input has an internal
active 25
μ
A pull-down and requires CMOS logic levels.
13
SCLK
Serial Clock
The SCLK terminal of the control IC is a bit (shift) clock for the SPI port. It transitions
one time per bit transferred when in operation. It is idle between command transfers. It
is 50% duty cycle, and has CMOS levels.
14
CS
Chip Select
This terminal is connected to a chip select output of the control IC. This input has an
internal active 25
μ
A pull-up and requires CMOS logic levels.
V
1
2
OUT0
IN1
OUT1
NC
IN2
OUT2
NC
SI
SCLK
CS
SO
MODE
IN0
IN0 & IN1
OUT6
IN6
OUT5
NC
IN4
OUT4
NC
IN3
OUT3
IN2 & IN3
IN7
OUT7
V
DD
IN4 & IN5
IN5
7
8
9
10
11
12
13
14
15
3
4
5
6
30
29
24
23
22
21
20
19
18
17
16
28
27
26
25
G
SINK
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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