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参数资料
| 型号： | MC33887VWR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 3/37页 |
| 文件大小： | 0K |
| 描述： | IC H-BRIDGE 5.0A W/CS 20-HSOP |
| 标准包装： | 750 |
| 应用： | DC 电机驱动器，H 桥式 |
| 评估套件： | 可供 |
| 输出数： | 1 |
| 电流 - 输出： | 5A |
| 电源电压： | 5 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.433"，11.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 20-HSOP |
| 包装： | 带卷 (TR) |
| 配用： | KIT33887PNBEVB-ND - KIT EVAL 33887 5A H-BRIDGE PQFN KIT33887DWBEVB-ND - KIT EVAL 33887 5A H-BRIDGE SOIC |
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PIN CONNECTIONS
PIN CONNECTIONS
Tab
AGND
FS
IN1
V+
V+
OUT1
OUT1
FB
PGND
PGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EN
IN2
D1
CCP
V+
OUT2
OUT2
D2
PGND
PGND
Tab
Figure 3. 33887 Pin Connections
Table 1. 33887 HSOP PIN DEFINITIONS
A functional description of each pin can be found in the Functional Pin DescriptionS section, page 21 .
Pin
1
2
Pin Name
AGND
FS
Formal Name
Analog Ground
Fault Status for H-Bridge
Definition
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
3
4 , 5, 16
6, 7
8
IN1
V+
OUT1
FB
Logic Input Control 1
Positive Power Supply
H-Bridge Output 1
Feedback for H-Bridge
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Positive supply connections
Output 1 of H-Bridge.
Current sensing feedback output providing ground referenced 1/375th
(0.00266) of H-Bridge high-side current.
9 – 12
13
PGND
D2
Power Ground
Disable 2
High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
14 , 15
17
18
OUT2
CCP
D1
H-Bridge Output 2
Charge Pump Capacitor
Disable 1
Output 2 of H-Bridge.
External reservoir capacitor connection for internal charge pump capacitor.
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
19
20
IN2
EN
Logic Input Control 2
Enable
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN
logic LOW = Sleep Mode).
Tab/Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
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