MC33888FB
DEVICE DESCRIPTION
Quad High Side and Octal Low Side Switch for Automotive
15
WATCHDOG AND FAILSAFE OPERATION
The watchdog is enabled and a timeout is started when the WAKE or RSTB transition from logic L to logic H. The WAKE input is
capable of being pulled up to VPWR with a series limiting resistance that limits the internal clamp current. The timeout is a
multiple of an internal oscillator . As long as the WDIN pin, or D15 of an incoming SPI message, is toggled within the minimum
watchdog timeout, wdto (or a divided value configured during a WDCSCR message), then the device will operate normally. If
the watchdog timeout occurs before the WD bit or WDIN pin is toggled, then the device will revert to a failsafe mode until the
device is reinitialized (if the FSI pin is left disconnected). During failsafe mode, all outputs will be off except for HS0 and HS2,
which will be driven on regardless of the state of the various direct inputs and modes. The device can be brought out of failsafe
mode by transitioning the WAKE and RSTB pins from logic H to logic L. In the event that the WAKE pin was not transitioned to a
logic H during normal operation and the watchdog times out, then the device can be brought out of failsafe by bringing the RSTB
to a logic L. If the FSI pin is tied to GND, then the watchdog, and therefore failsafe operation, will be disabled (see TABLE 4).
Table 4
FAILSAFE OPERATION
X: don
’
t care
S: state determined by SPI and/or Direct Input configurations.
Assumptions: Normal operating Voltage and Junction Temperatures, FSI pin floating.
DEFAULT MODE
The default mode describes the state of the device after first applying battery or a reset transition from logic L to H prior to SPI
communication. In the default mode, all of the outputs will be off (assuming that the direct inputs ILS and IHSx, and the WAKE
pins are at logic L). All of the specific pin functions will operate as though all of the addressable configuration register bits were
set to logic L. This means, for example, that all of the LS outputs will be controllable by the ILS pin, and that all HS outputs will be
controllable via their respective IHS pins. During the Default Mode, all of the HS drivers will default with the open load detection
enabled. All of the low side drivers will default with the open load detection disabled. This mode allows limited control of the
QHSOLSS with the direct inputs in the absence of a SPI.
FAULT LOGIC REQUIREMENTS
The QHSOLSS indicates all of the following faults as they occur: over-temperature fault, open-load fault, over-current fault and
an over-voltage fault. All of these faults, with the exception of the over-voltage, are output specific. The over-voltage fault is a
global fault
. The over-current fault is only reported for the low side outputs.
The QHSOLSS low-side outputs incorporate an internal fault filter
“
Tdly(flt)
”
.The fault timer filters noise and switching transients
for over-current faults (when the output is on) and open load faults (when the output is off).
All faults are latched and indicated
For More Information On This Product,
WAK
E
RSTB
WDTO
HS0
HS2
OTHER
LSx,
HSx
COMMENTS
L
L
X
OFF
OFF
OFF
Device is in Sleep Mode
H
L
NO
OFF
OFF
OFF
All outputs are OFF, when RSTB
transitions to logic H, device is in
Default
H
L
YES
ON
ON
OFF
Failsafe. Device reset into Default
mode by transitioning WAKE to logic L
L
H
NO
S
S
S
Device in Normal Operating mode
L
H
YES
ON
ON
OFF
Failsafe. Device reset into Default
mode by transitioning RSTB to logic L
H
H
NO
S
S
S
Device in Normal Operating Mode
H
H
YES
ON
ON
OFF
Failsafe. Device reset into Default
mode by transitioning RSTB & WAKE
to logic L
F
Freescale Semiconductor, Inc.
n
.