参数资料
型号: MC33910BACR2
厂商: Freescale Semiconductor
文件页数: 42/90页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP 32LQFP
标准包装: 2,000
应用: 系统基础芯片
电流 - 电源: 4.5mA
电源电压: 5.5 V ~ 27 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 带卷 (TR)
MC33910G5AC/MC3433910G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
High Side Control Register - HSCR
This register controls the operation of the high side drivers.
Writing to this register returns the High Side Status Register
(HSSR).
Table 19. High Side Control Register - $6
0 = Normal
Timing Control Register - TIMCR
This register allows to configure the watchdog, the cyclic
sense and Forced Wake-up periods. Writing to the Timing
Control Register (TIMCR) will also return the Watchdog
C3
C2
C1
C0
Status Register (WDSR).
Write
PWMHS2
PWMHS1
HS2
HS1
Table 21. Timing Control Register - $A
Reset
Value
0
0
0
0
C3
C2
WD2
C1
WD1
C0
WD0
Reset
Condition
POR
POR, Reset mode, ext_reset, HSx
over-temp or (VSOV & HVSE)
Write
CS/WD
CYST2
CYST1
CYST0
PWMHSx - PWM Input Control Enable.
This write-only bit enables/disables the PWMIN input pin
to control the respective high side switch. The corresponding
Reset
Value
Reset
Condition
-
-
0
0
POR
0
high side switch must be enabled (HSx bit).
1 = PWMIN input controls HSx output.
0 = HSx is controlled only by SPI.
HSx - HSx Switch Control.
This write-only bit enables/disables the corresponding
high side switch.
1 = HSx switch on.
0 = HSx switch off.
High Side Status Register - HSSR
This register returns the status of the high side switches
and is also returned when writing to the HSCR.
Table 20. High Side Status Register - $6/$7
CS/WD - Cyclic Sense or Watchdog prescaler select
This write-only bit selects which prescaler is being written
to, the Cyclic Sense/Forced Wake-up prescaler or the
Watchdog prescaler.
1 = Cyclic Sense/Forced Wake-up Prescaler selected
0 = Watchdog Prescaler select
WDx - Watchdog Prescaler
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 22 . This configuration is valid only if
windowing watchdog is active.
Table 22. Watchdog Prescaler
S3
S2
S1
S0
WD2
WD1
WD0
Prescaler Divider
Read
HS2OP
HS2CL
HS1OP
HS1CL
0
0
0
0
0
1
1
2
High Side thermal shutdown
A thermal shutdown of the high side drivers is indicated by
setting all HSxOP and HSxCL bits simultaneously.
HSxOP - High Side Switch Open-Load Detection
This read-only bit signals that the high side switches are
conducting current below a certain threshold indicating
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
4
6
8
10
12
14
possible load disconnection.
1 = HSx Open Load detected (or thermal shutdown)
0 = Normal
HSxCL - High Side Current Limitation
This read-only bit indicates that the respective high side
switch is operating in current limitation mode.
1 = HSx in current limitation (or thermal shutdown)
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 44 ).
This option is only active if one of the high side switches is
enabled when entering in Stop or Sleep mode. Otherwise, a
timed wake-up is performed after the period shown in
33910
Analog Integrated Circuit Device Data
42
Freescale Semiconductor
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