参数资料
型号: MC33910BACR2
厂商: Freescale Semiconductor
文件页数: 83/90页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP 32LQFP
标准包装: 2,000
应用: 系统基础芯片
电流 - 电源: 4.5mA
电源电压: 5.5 V ~ 27 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 带卷 (TR)
MC33910BAC / MC34910BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
configuration register (CFR) (see Configuration Register -
CFR ).
This option is only active if the high side switch is enabled
when entering in Stop or Sleep mode. Otherwise a timed
wake-up is performed after the period shown in Table 51 .
1 = Last reset caused by watchdog timeout
0 = None
WDERR - Watchdog Error
This read-only bit signals the detection of a missing
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The windowing function is
disabled.
Table 51. Cyclic Sense Interval
CYSX8 (123) CYST2 CYST1 CYST0
Interval
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
No Cyclic Sense
20 ms
40 ms
60 ms
80 ms
100 ms
120 ms
140 ms
160 ms
320 ms
480 ms
640 ms
800 ms
960 ms
1120 ms
WDOFF - Watchdog Off
This read-only bit signals that the watchdog pin connected
to GND and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
1 = Watchdog is disabled
0 = Watchdog is enabled
WDWO - Watchdog Window Open
This read-only bit signals when the watchdog window is
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
1 = Watchdog window open
0 = Watchdog window closed
Analog Multiplexer Control Register - MUXCR
Notes
123. bit CYSX8 is located in configuration register (CFR)
Watchdog Status Register
This register controls the analog multiplexer and selects
the divider ration for the L1 input divider.
Table 53. Analog Multiplexer Control Register -$C
This register returns the watchdog status information and
C3
C2
C1
C0
is also returned when writing to the TIMCR.
Table 52. Watchdog Status Register - $A/$B
Write
Reset Value
L1DS
1
MX2
0
MX1
0
MX0
0
Read
S3
WDTO
S2
WDERR
S1
WDOFF
S0
WDWO
Reset Condition
POR
POR, Reset mode or ext_reset
L1DS - L1 Analog Input Divider Select
WDTO - Watchdog Time Out
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
watchdog within the window closed.
This write-only bit selects the resistor divider for the L1
analog input. Voltage is internally clamped to VDD.
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
Any access to this register or the TIMCR will clear the
WDTO bit.
33910
Analog Integrated Circuit Device Data
83
Freescale Semiconductor
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