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参数资料
| 型号： | MC33932VW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 3/28页 |
| 文件大小： | 0K |
| 描述： | IC H-BRIDGE THROTTLE CTRL 44HSOP |
| 标准包装： | 30 |
| 类型： | 半桥 |
| 输入类型： | 非反相 |
| 输出数： | 2 |
| 导通状态电阻： | 120 毫欧 |
| 电流 - 峰值输出： | 5A |
| 电源电压： | 8 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-BSSOP（0.433"，11.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 44-HSOP |
| 包装： | 管件 |
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PIN CONNECTIONS
PIN CONNECTIONS
D1
FBA
EN/D2
VPWRA
VPWRA
VPWRA
OUT1
OUT1
OUT1
PGNDA
PGNDA
PGNDB
PGNDB
OUT4
OUT4
OUT4
VPWRB
VPWRB
CCPB
IN4
IN3
SFB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AGNDA
Tab
H-BRIDGE A
H-BRIDGE B
Tab
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SFA
IN1
IN2
CCPA
VPWRA
VPWRA
OUT2
OUT2
OUT2
PGNDA
PGNDA
PGNDB
PGNDB
OUT3
OUT3
OUT3
VPWRB
VPWRB
VPWRB
EN/D4
FBB
D3
VPWRA
NC
D1
FBA
EN/D2
NC
NC
NC
VPWRA
OUT1
OUT1
PGNDA
PGNDA
NC
PGNDB
PGNDB
OUT4
OUT4
VPWRB
CCPB
NC
NC
IN4
IN3
SFB
VPWRB
AGNDB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
AGNDA
VPWRA
SFA
IN1
IN2
NC
NC
CCPA
VPWRA
OUT2
OUT2
PGNDA
PGNDA
NC
PGNDB
PGNDB
OUT3
OUT3
VPWRB
NC
NC
NC
EN/D4
FBB
D3
NC
VPWRB
AGNDB
44 HSOP
Transparent Top View
54 SOICW-EP
Transparent Top View
Figure 3. 33932 Pin Connections
A functional description of each pin can be found in the Functional Description section beginning on Functional Description .
Table 1. 33932 Pin Definitions
Pin
HSOP
(VW)
1
Pin
SOICW-EP
(EK)
3
Pin Name
D1
Pin
Function
Logic Input
Formal Name
Disable Input 1
(Active High)
Definition
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated.
Schmitt trigger input with ~80 ? A source so default
condition = disabled.
2
4
FBA
Analog
Feedback
H-Bridge A load current feedback output provides ground
Output
referenced 0.24% of the high side output current. (Tie to GND
through a resistor if not used.)
3
5
EN/D2
Logic Input
Enable Input
When EN/D2 is logic HIGH, H-Bridge A is operational. When EN/
D2 is logic LOW, the H-Bridge A outputs are tri-stated and H-
Bridge A is placed in Sleep Mode. (logic input with ~ 80 ? A sink so
default condition = Sleep Mode.)
4-6, 39, 40
1, 9, 46, 53
VPWRA
Power Input
Positive Power
These pins must be connected together physically as close as
Supply
possible and directly soldered down to a wide, thick, low
resistance supply plane on the PCB.
7-9
10, 11
OUT1
Power
H-Bridge Output 1
H-Bridge A source of HS1 and drain LS1.
Output
33932
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
3
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