参数资料
型号: MC33932VW
厂商: Freescale Semiconductor
文件页数: 4/28页
文件大小: 0K
描述: IC H-BRIDGE THROTTLE CTRL 44HSOP
标准包装: 30
类型: 半桥
输入类型: 非反相
输出数: 2
导通状态电阻: 120 毫欧
电流 - 峰值输出: 5A
电源电压: 8 V ~ 28 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 44-BSSOP(0.433",11.00mm 宽)裸露焊盘
供应商设备封装: 44-HSOP
包装: 管件
PIN CONNECTIONS
Table 1. 33932 Pin Definitions (continued)
Pin
HSOP
(VW)
10, 11, 34,
35
Pin
SOICW-EP
(EK)
12, 13, 42,
43
Pin Name
PGNDA
Pin
Function
Power
Ground
Formal Name
Power Ground
Definition
High-current power ground pins must be connected together
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB. PGNDA
should be connected to PGNDB with a low-impedance path.
12, 13, 32,
33
15, 16, 39,
40
PGNDB
Power
Ground
Power Ground
High-current power ground pins must be connected together
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB. PGNDB
should be connected to PGNDA with a low-impedance path.
14-16
17, 18
OUT4
Power
H-Bridge Output 4
H-Bridge B Source of HS2 and drain of LS2.
Output
17, 18,
26-28
19, 26, 28,
36
VPWRB
Power Input
Positive Power
Supply
These pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low
resistance supply plane on the PCB.
19
20
CCPB
Analog
Charge Pump
External reservoir capacitor connection for H-Bridge B internal
Output
Capacitor
charge pump; connected to VPWRB. Allowable values are 30 to
100 nF. Note: This capacitor is required for the proper
performance of the device.
20
21
22
23
24
25
IN4
IN3
SFB
Logic Input
Logic Input
Logic
Input 4
Input 3
Status Flag B
Logic input control of OUT4.
Logic input control of OUT3.
H-Bridge B open drain active LOW Status Flag output (requires
Output -
Open Drain
(Active Low)
an external pull-up resistor to V DD . Maximum permissible load
current < 0.5 mA. Maximum V SFLOW < 0.4 V at 0.3 mA. Maximum
permissible pull-up voltage < 7.0 V.)
23
30
D3
Logic Input
Disable Input 3
(Active High)
When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated.
Schmitt trigger input with ~80 ? A source so default condition =
disabled.
24
31
FBB
Analog
Feedback B
H-Bridge B load current feedback output provides ground
Output
referenced 0.24% of the high side output current. (Tie to GND
through a resistor if not used.)
25
32
EN/D4
Logic Input
Enable Input
When EN/D4 is logic HIGH, H-Bridge B is operational. When EN/
D4 is logic LOW, the H-Bridge B outputs are tri-stated and H-
Bridge B is placed in Sleep Mode. (logic input with ~ 80 ? A sink so
default condition = Sleep Mode.)
29-31
37, 38
OUT3
Power
H-Bridge Output 3
H-Bridge B Source of HS1 and drain of LS1.
Output
36-38
44, 45
OUT2
Power
H-Bridge Output 2
H-Bridge A source of HS2 and drain of LS2.
Output
41
47
CCPA
Analog
Charge Pump
External reservoir capacitor connection for H-Bridge A internal
Output
Capacitor
charge pump; connected to VPWRA. Allowable values are 30 to
100 nF. Note: This capacitor is required for the proper
performance of the device.
42
43
50
51
IN2
IN1
Logic Input
Logic Input
Input 2
Input 1
Logic input control of OUT2.
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1
is set to VPWRA, and when IN1 is logic LOW, OUT1 is set to
PGNDA. (Schmitt trigger Input with ~ 80 ? A source so default
condition = OUT1 HIGH.)
33932
Analog Integrated Circuit Device Data ?
4
Freescale Semiconductor
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