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| 型号： | MC33981BPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 36/40页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HI SIDE SINGLE 16-PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | PWM |
| 输出数： | 1 |
| 导通状态电阻： | 4 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-PowerDFN |
| 供应商设备封装： | 16-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
INTRODUCTION
This thermal addendum is provided as a supplement to the 33981 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
PACKAGING AND THERMAL CONSIDERATIONS
This package is a dual die package. There are two heat sources in the package
independently heating with P 1 and P 2 . This results in two junction temperatures,
T J1 and T J2 , and a thermal resistance matrix with R ? JAmn .
For m , n = 1, R ? JA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P 1 .
For m = 1, n = 2, R ? JA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P 2 . This applies to
R ? J21 and R ? J22, respectively.
33981
16-PIN
PQFN
98ARL10521D
16-PIN PQFN
12 MM X 12 MM
Note For package dimensions, refer to
98ARL10521D.
T J1
T J2
=
R ? JA11
R ? JA21
R ? JA12
R ? JA22
.
P 1
P 2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
STANDARDS
Table 8. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [ ? C/W]
Thermal
Resistance
? ? JA mn (1) , (2)
m = 1,
n =1
22
m = 1, n = 2
m = 2, n = 1
18
m = 2,
n =2
41
? ? JB mn
7.0
4.0
27
0.2 mm spacing
between PCB pads
? ? JA mn (1) , (4)
62
48
81
? ? JC mn
<1.0
0.0
1.0
Notes
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and ?
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
0.2 mm spacing
between PCB pads
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
Figure 44. Surface mount for power PQFN
with exposed pads
exposed pad, “infinite” heat sink attached to exposed pad.
33981
Analog Integrated Circuit Device Data ?
36
Freescale Semiconductor
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