参数资料
| 型号： | MC34717EPR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | IC CONVERTER DDR 26QFN |
| 标准包装： | 2,500 |
| 应用： | 转换器，DDR |
| 输入电压： | 3 V ~ 6 V |
| 输出数： | 2 |
| 输出电压： | 0.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 26-VFQFN 裸露焊盘 |
| 供应商设备封装： | 26-QFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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TYPICAL APPLICATIONS
resistors will affect the accuracy of the system and must be
1% accurate resistors.
To achieve this tracking configuration, the master voltage
must be connected in the way shown and cannot be directly
connected to the VREFIN terminal.
and R 2 = R 4 + R 5 ) . The master’s feedback resistor divider
would be (R 3 +R 4 ) and R 5 . All five resistors will affect the
accuracy of the system and must be 1% accurate resistors.
To achieve this tracking configuration, the master voltage
must be connected in the way shown and cannot be directly
connected to the VREFIN terminal.
V MASTER
V MASTER
V BG
VREFIN
Reference
R3
R4
To INV- of
Vmaster
V BG
VREFIN
R3
R4
To INV- of
Vmaster
selector
V SLAVE
Reference
selector
R5
V SLAVE
+
EA
-
INV
Rs
Cs
C X
R F
C F
R 1
R 2
C O
+
EA
-
INV
Rs
Cs
C X
R F
C F
R 1
R 2
C O
COMP
Figure 12. Ratiometric Tracking Circuit Connections
EQUATIONS
COMP
Figure 14. Co-incidental Tracking Circuit Connections
EQUATIONS
?
V M = V BG_M [1+(R 3 +R 4 )/R 5 ]
? V M = V BG_M (1+R 3 /R 4 )
? V REFIN = V M * R 4 /(R 3 +R 4 )
? V REFOUT = V REFIN
? V S = V REFOUT (1+R 1 /R 2 ) = V M * R 4 /(R 3 +R 4 )*(R 2 +R 1 )/R 2 ,
if V REFOUT < V BG_S
? V S = V BG_S (1+R 1 /R 2 ), if V REFOUT ≥ V BG_S
Figure 13. Ratiometric Tracking Plot
CO-INCIDENTAL TRACKING CIRCUIT
CONFIGURATION:
Connect a three resistor divider to the master voltage (V M )
and Route the upper tap point of the divider to the VREFIN
terminal, resistors R 3 , R 4 , and R 5 as shown in Figure 14 . This
resistor divider must be the same ratio as the slave output’s
(V S ) feedback resistor divider, which in turn connects to the
INV- terminal, resistors R 1 and R 2 below ( Condition: R 1 = R 3
? V REFIN = V M *(R 4 +R 5 )/(R 3 +R 4 +R 5 )
? V REFOUT = V REFIN
? V S = V REFOUT (1+R 1 /R 2 ) = V M *(R 4 +R 5 )/
(R 3 +R 4 +R 5 )*(R 2 +R 1 )/R 2 = V M if V REFOUT < V BG_S
? V S = V BG_S (1+R 1 /R 2 ), if V REFOUT ≥ V BG_S
Figure 15. Co-incidental Tracking Plot
Not-DDR Mode (Source Only Mode) is the case when no
tracking is needed. VREFIN should be connected to VDDI
and the reference selection block will use the internal band
gap voltage as the error amplifier’s reference voltage.
A user can potentially apply a voltage to the VREFIN
terminal directly or through a resistor divider to get a buffered
output for use in the application. The condition here is, the
voltage applied to the VREFIN terminal is greater than V BG to
guarantee that the reference selection block will not switch
back to the V REFOUT voltage.
34717
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
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