MC34910BAC (Freescale) PDF资料下载 Datasheet(60/90 页)

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参数资料

型号：	MC34910BAC
厂商：	Freescale Semiconductor
文件页数：	60/90页
文件大小：	0K
描述：	IC SYSTEM BASIS CHIP LIN 32-LQFP
标准包装：	250
应用：	系统基础芯片
电流 - 电源：	4.5mA
电源电压：	5.5 V ~ 27 V
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	32-LQFP
供应商设备封装：	32-LQFP（7x7）
包装：	托盘

MC33910BAC / MC34910BAC

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 34. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V SUP ≤ 18 V, -40°C ≤ T A ≤ 125°C for the 33910 and -40°C ≤ T A ≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T A = 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

L1 INPUT

Wake-up Filter Time

t WUF

8.0

20

38

μ s

STATE MACHINE TIMING

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)

and Stop Mode Activation (107)

Normal Request Mode Timeout (see Figure 33 )

t STOP

t NR TOUT

–

110

–

150

5.0

205

μ s

ms

Delay Between SPI Command and HS Turn On (108)

t S- ON

μ s

9.0 V < V SUP < 27 V

Delay Between SPI Command and HS Turn Off (108)

9.0 V < V SUP < 27 V

t S- OFF

–

–

–

–

10

10

μ s

Delay Between Normal Request and Normal Mode After a Watchdog Trigger

Command (Normal Request mode) (107)

t SNR2N

–

–

10

μ s

Delay Between CS Wake-up ( CS LOW to HIGH) in Stop Mode and:

μ s

Normal Request mode, VDD ON and RST HIGH

First Accepted SPI Command

t WUCS

t WUSPI

9.0

90

15

—

80

N/A

Minimum Time Between Rising and Falling Edge on the CS

t 2CS

4.0

—

—

μ s

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC (109) , (110)

Duty Cycle 1: D1 = t BUS_REC(MIN) /(2 x t BIT ), t BIT = 50 μs

7.0 V ≤ V SUP ≤ 18 V

Duty Cycle 2: D2 = t BUS_REC(MAX) /(2 x t BIT ), t BIT = 50 μs

7.6 V ≤ V SUP ≤ 18 V

D1

D2

0.396

—

—

—

—

0.581

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4

KBIT/SEC (109) , (111)

Duty Cycle 3: D3 = t BUS_REC(MIN) /(2 x t BIT ), t BIT = 96 μs

7.0 V ≤ V SUP ≤ 18 V

Duty Cycle 4: D4 = t BUS_REC(MAX) /(2 x t BIT ), t BIT = 96 μs

7.6 V ≤ V SUP ≤ 18 V

D3

D4

0.417

—

—

—

—

0.590

μ s

μ s

Notes

107. This parameter is guaranteed by process monitoring but, not production tested.

108. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load.

109. Bus load R BUS and C BUS 1.0 nF / 1.0 k Ω , 6.8 nF / 660 Ω , 10 nF / 500 Ω . Measurement thresholds: 50% of TXD signal to LIN signal

threshold defined at each parameter. See Figure 27 .

110. See Figure 28 .

111. See Figure 29 .

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

60

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