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参数资料
| 型号： | MC34910BAC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 73/90页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM BASIS CHIP LIN 32-LQFP |
| 标准包装： | 250 |
| 应用： | 系统基础芯片 |
| 电流 - 电源： | 4.5mA |
| 电源电压： | 5.5 V ~ 27 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 托盘 |
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MC33910BAC / MC34910BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
WINDOW WATCHDOG
The 33910 includes a configurable window watchdog
which is active in Normal mode. The watchdog can be
configured by an external resistor connected to the WDCONF
pin. The resistor is used to achieve higher precision in the
timebase used for the watchdog.
SPI clears are performed by writing through the SPI in the
MOD bits of the MCR.
During the first half of the SPI timeout watchdog clears are
not allowed; but after the first half of the PSPI-timeout window
the clear operation opens. If a clear operation is performed
outside the window, the 33910 will reset the MCU, in the
same way as when the watchdog overflows.
in the WDSR will be set. This condition is only detected
during Reset mode.
If neither a resistor nor a connection to ground is detected,
the watchdog falls back to the internal lower precision
timebase of 150 ms (typ.) and signals the faulty condition
through the WDSR.
The watchdog timebase can be further divided by a
prescaler which can be configured by the TIMCR. During
Normal Request mode, the window watchdog is not active
but there is a 150 ms (typ.) timeout for leaving the Normal
Request mode. In case of a timeout, the 33910 will enter into
Reset mode, resetting the microcontroller before entering
again into Normal Request mode.
HIGH SIDE OUTPUT PINS HS1 AND HS2
WINDOW CLOSED
NO WATCHDOG CLEAR
ALLOWED
WD TIMING X 50%
WINDOW OPEN
FOR WATCHDOG
CLEAR
WD TIMING X 50%
These outputs are two high side drivers intended to drive
small resistive loads or LEDs incorporating the following
features:
? PWM capability (software maskable)
? Open load detection
? Current limitation
? Over-temperature shutdown (with maskable interrupt)
? High-voltage shutdown (software maskable)
? Cyclic sense
The high side switches are controlled by the bits HS1:2 in
WD PERIOD (t PWD )
WD TIMING SELECTED BY REGISTER
ON WDCONF PIN
Figure 37. Window Watchdog Operation
To disable the watchdog function in Normal mode the user
must connect the WDCONF pin to ground. This measure
effectively disables Normal Request mode. The WDOFF bit
the High Side Control Register (HSCR).
PWM Capability (direct access)
Each high side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
If both the bits HS1 and PWMHS1 are set in the High Side
Control Register (HSCR), then the HS1 driver is turned on if
the PWMIN pin is high and turned of if the PWMIN pin is low.
This applies to HS2 configuring HS2 and PWMHS2 bits.
33910
Analog Integrated Circuit Device Data
73
Freescale Semiconductor
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