参数资料
型号: MC34921AER2
厂商: Freescale Semiconductor
文件页数: 15/36页
文件大小: 0K
描述: IC MOTOR DRVR PWM DC DUAL 64LQFP
标准包装: 1,500
应用: DC 电机驱动器,步进电机驱动器,H 桥式
输出数: 2
电流 - 输出: ±4.5A
电压 - 负载: 0 V ~ 38 V
电源电压: 4.8 V ~ 5.2 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP 裸露焊盘
供应商设备封装: 64-LQFP EP(10x10)
包装: 带卷 (TR)
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 16 V ≤ B+ ≤ 34 V, 0 ° C ≤ T A ≤ 70 ° C, and 0 ° C ≤ T J ≤ 100 ° C unless otherwise noted.
Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Supervisor Circuitry
RST Delay
t delay (RST)
t SCLK
V 5.0 = ≥ +4.9 V
RST Filter Time
V 5.0 = 5.0 V
RST Fall Time
t filter
t f
128
3.25
128
μ s
ns
V 5.0 = 5.0 V, C L = 100 pF, I PULLUP = 0.75 mA(external), 90% to 10% of
7.0
20
V 5.0
External Input Low to RST Pulled Low
t slpl
ns
V 5.0 = 5.0 V (25)
26
60
Analog Encoder Interface Variable Gain Stage
Adjustable Gain (Ideal)
Settings S = 0 to 15, Default 0
Settings S = 16 to 31, Default 0
G (Ideal)
(1.0+0.1 * S)
(1.0+0.1 * [S-16]) / 0.375
Gain
G
V/V
Setting = 0
Setting = 31
Gain Step Factor Tolerance
Gain Step Size Gs/G(s- 1 ) S = 1 to 31
GSF
0.8
6.0
1.01
1.0
6.6
1.02
1.2
7.2
1.2
V/V
Analog Encoder Interface Digital Signal Conversion Stage
Operating Frequency
Comparator Filter Time (24)
Filter Configuration Bit Set to 0
Filter Configuration Bit Set to 1
f OP(MAX)
t filter
0
3.0
6.0
15
4.0
7.0
kHz
SCLK
Cycles
ADC
Sample and Hold Acquisition Time
t sh
t SCLK
A/D Speed Bit = 0
A/D Speed Bit = 1
Conversion Time (Return Word Clocked Out Immediately Following t c )
A/D Speed Bit = 0
A/D Speed Bit = 1
t c
15
31
16
32
48
96
t SCLK
Master Oscillator
Operating Frequency
f OP
kHz
B+ ≥ 12 V
150
200
250
Notes
24. Guaranteed by design.
25. See Figure 6, RST Timing , page 17 .
34921
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
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