参数资料
型号: MC34921AER2
厂商: Freescale Semiconductor
文件页数: 29/36页
文件大小: 0K
描述: IC MOTOR DRVR PWM DC DUAL 64LQFP
标准包装: 1,500
应用: DC 电机驱动器,步进电机驱动器,H 桥式
输出数: 2
电流 - 输出: ±4.5A
电压 - 负载: 0 V ~ 38 V
电源电压: 4.8 V ~ 5.2 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP 裸露焊盘
供应商设备封装: 64-LQFP EP(10x10)
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CONFIG MODE:
Configuration mode is the mode in which the IC is programmed or configured by the external digital subsystem via the serial
interface (i.e., MOSI, MISO, SCLK, CE).
Table 12. CONFIG Mode Input Frame Programming Model
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mtest1 Mtest0
cal4
(MSB)
cal3
cal2
cal1
cal0
(LSB)
ANALOG
_TEST
MODE
caladdr caladdr
1 0
Filter
DC SS
A/D
Speed
sleep
IREQ
config
Table 13. CONFIG Input Frame Bit Allocation (32)
Bit
15 –14
13 –9
8
7 –6
5
4
3
2
1
0
Bit Name
Mtest[1:0]
cal[4:0]
ANALOG_TEST
MODE
caladdr[1:0]
Filter
DC SS
A/D Speed
sleep
IREQ
config
Bit Description
Reserved for Freescale test. Set to [10].
Data for various calibration registers.
Routes A and B output of analog encoder interface to AN0 and AN1, respectively. Used only for user
development and verification. Do not use in normal operation.
Determines the calibration register, as identified in Table 14 below, the calibration data in the cal[4:0] (Bits
13 –9) bits is latched in.
Determines the number of SCLK edges used to filter the DENCA and DENCB signals coming from the Digital
Signal Generation stage of the analog encoder interface. This digital filter filters the DENCA and DENCB
signals made available to the serial output frame.
Determines if Motor Driver C operates in DC motor or step motor mode. Implicitly determines whether
HSOUTx or LSOUTx are available. In DC motor mode, LSOUTx are available; in step motor mode, HSOUTx
are available.
Determines how many SCLK edges are required for conversion. This allows the use of a faster SCLK but still
maintains A/D conversion accuracy.
When asserted, causes the 34921 to enter a power-down state, and minimize power consumption.
Causes the next output frame sent to the host to contain internal information from the 34921.
The input frame can be either a configuration frame or a normal frame. Bit 0 determines the type of frame being
received. Bit 0 = 1 is a configuration mode input frame.
Notes
32. All defaults = 0 at power up.
Table 14. Calibration Register Addressing
caladdr0
0
1
0
1
caladdr1
0
0
1
1
Channel A gain
Channel A offset
Channel B gain
Channel B offset
Register
34921
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
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