参数资料
型号: MC56F8014VFAE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 0-BIT, 8 MHz, OTHER DSP, PQFP32
封装: ROHS COMPLIANT, PLASTIC, LQFP-32
文件页数: 116/124页
文件大小: 1681K
代理商: MC56F8014VFAE
56F8014 Information
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
91
Figure 8-4 GPIOD Register Map Summary
Part 9 Joint Test Action Group (JTAG)
9.1 56F8014 Information
Please contact your Freescale sales representative or authorized distributor for device/package-specific
BSDL information.
The TRST pin is not available in this package. The pin is tied to VDD in the package.
The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high
for five rising edges of TCK, as described in the 56F8000 Peripheral User Manual.
Part 10 Specifications
10.1 General Characteristics
The 56F8014 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The
term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels, combined with the ability to receive 5V levels without damage.
Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum
is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to
the device.
Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40C to
125C ambient temperature over the following supply ranges:
VSS =VSSA=0V,VDD =VDDA = 3.0–3.6V, CL < 50pF, fOP = 32MHz
RS
Reset
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