MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor
48
6.2.4
Flash Lockout Recovery without Mass Erase
6.2.4.1
Without Presenting Back Door Access Keys to the Flash Unit
A user can unsecure a secured device by programming the word 0x0000 into program flash location 0x00 7FF7. After
completing the programming, the JTAG TAP controller and the device must be reset to return to normal unsecured operation.
The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word 0x0000 into
program flash location 0x00 7FF7. You can do so, for example, by toggling a specific pin or downloading a user-defined key
through serial interfaces.
NOTE
Flash contents can be programmed only from ones to zeroes.
6.2.4.2
Presenting Back Door Access Key to the Flash Unit
The user can temporarily bypass security through a “back door” access scheme, using a four-word key to temporarily unlock
the flash. “Back door” access requires support from the embedded software. This software would typically permit an external
user to enter the four-word code through one of the communications interfaces and then use it to attempt the unlock sequence.
If the input matches the four-word code stored at location 0x00 7FFC–0x00 7FFF in the flash memory, the device immediately
becomes unsecured (at runtime) and internal memory is accessible via the JTAG/EOnCE port. Refer to the device’s reference
manual for details. The key must be entered in four consecutive accesses to the flash, so this routine should be designed to run
in RAM.
6.3
Product Analysis
To analyze a product’s failures in the field, the recommended method of unsecuring a secured device appears in
Section 6.2.4.2,to access the subroutines in flash memory. An alternative method for performing analysis on a secured device is to mass-erase
and reprogram the flash memory with the original code, but also to modify or not program the security word.
7
Specifications
7.1
General Characteristics
The MC56F825x/MC56F824x is fabricated in high-density, low-power, low-leakage CMOS process with 5 V–tolerant,
TTL-compatible digital inputs. The term 5 V–tolerant refers to the capability of an I/O pin, built on a 3.3 V–compatible process
technology, to withstand a voltage up to 5.5 V without damaging the device. Many systems have a mixture of devices designed
for 3.3 V and 5 V power supplies. In such systems, a bus may carry both 3.3 V–compatible and 5 V–compatible I/O voltage
levels (a standard 3.3 V I/O is designed to receive a maximum voltage of 3.3 V
± 10% during normal operation without causing
damage). This 5 V–tolerant capability therefore combines the power savings of 3.3 V I/O levels with the ability to receive 5 V
levels without damage.
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage
or electrical fields. However, normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate voltage level.