参数资料
型号: MC56F8247VLH
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-026BCD, LQFP-64
文件页数: 66/88页
文件大小: 4050K
代理商: MC56F8247VLH
Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
69
7.25.1
Equivalent Circuit for ADC Inputs
Figure 31 illustrates the ADC input circuit during sample and hold. S1 and S2 are always opened/closed at non-overlapping
phases and operate at the ADC clock frequency. Equivalent input impedance, when the input is selected, is as follows:
(2 x k / ADCClockRate x Cgain ) + 100 ohms + 125 ohms
Eqn. 1
where k =
1 for first sample
6 for subsequent samples
and Cgain is as described in note 4 below.
1. Parasitic capacitance due to package, pin-to-pin, and pin-to-package base coupling: 1.8 pF
Input impedance
XIN
—See Figure 31
—Ohms
AC Specifications9 (gain of 1x, 2x, 4x and fADC ≤ 10 MHz)4
Signal-to-noise ratio
SNR
59
dB
Total Harmonic Distortion
THD
64
dB
Spurious Free Dynamic Range
SFDR
65
dB
Signal-to-noise plus distortion
SINAD
59
dB
Effective Number Of Bits
ENOB
9.5
Bits
1 All measurements were made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground
2 Includes power-up of ADC and VREF
3 ADC clock cycles
4 Speed register setting must be 00 for ADC clock ≤ 5 MHz, 01 for 5 MHz < ADC clock ≤ 12 MHz, and 10 for ADC clock > 12 MHz
5 INL and DNL measured from VIN = VREFL to VIN = VREFH
6 LSB = Least Significant Bit = 0.806 mV at x1 gain
7 Pin groups are detailed following Table 17.
8 The current that can be injected or sourced from an unselected ADC signal input without affecting the performance of the ADC
9 ADC PGA gain is x1
Table 41. ADC Parameters1 (continued)
Parameter
Symbol
Min
Typ
Max
Unit
1
2
3
Analog input
S1
S2
C1
S/H
C1: Single Ended Mode
2XC1: Differential Mode
(VREFHx - VREFLx ) / 2
125-ohm ESD
resisto
r
S2
S1
Channel Mux
equivalent resistance
100 ohms
C1: Single Ended Mode
2XC1: Differential Mode
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