参数资料
型号: MC56F8256VLF
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP48
封装: 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48
文件页数: 57/88页
文件大小: 4050K
代理商: MC56F8256VLF
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor
60
7.17
Reset, Stop, Wait, Mode Select, and Interrupt Timing
NOTE
All address and data buses described here are internal.
Figure 19. GPIO Interrupt Timing (Negative Edge-Sensitive)
7.18
Queued Serial Peripheral Interface (SPI) Timing
Table 33. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1 In the formulas, T = system clock cycle and T
osc = oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns.
At 4 MHz (used coming out of reset and stop modes), T = 250 ns.
2 Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical Min
Typical Max
Unit
See Figure
Minimum RESET Assertion Duration 3
3 This minimum number guarantees that a reliable reset occurs.
tRA
4T
ns
Minimum GPIO pin Assertion for Interrupt
tIW
2T
ns
RESET deassertion to First Address Fetch
tRDA
96TOSC + 64T
97TOSC + 65T
ns
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
tIF
—6T
ns
Table 34. SPI Timing1
Characteristic
Symbol
Min
Max
Unit
Refer to
Cycle time
Master
Slave
tC
125
62.5
ns
Enable lead time
Master
Slave
tELD
31
ns
Enable lag time
Master
Slave
tELG
125
ns
Clock (SCK) high time
Master
Slave
tCH
50
31
ns
Clock (SCK) low time
Master
Slave
tCL
50
31
ns
GPIO pin
(Input)
tIW
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