参数资料
型号: MC56F8347VPY60
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封装: PLASTIC, LQFP-160
文件页数: 23/172页
文件大小: 2620K
代理商: MC56F8347VPY60
Stop and Wait Mode Disable Function
56F8347 Technical Data, Rev.11
Freescale Semiconductor
119
Preliminary
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
6.8 Stop and Wait Mode Disable Function
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest
power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering
Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E
system clock must be set equal to the oscillator output.
Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those
instructions, write to the SIM control register (SIM_CONTROL), described in Part 6.5.1. This procedure
can be on either a permanent or temporary basis. Permanently assigned applications last only until their
next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and
the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within
the SIM itself by writing to the SIM_CONTROL register and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced
to permit proper operation of the device. A POR reset is first extended for 221 clock cycles to permit
stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated. It is
then followed by a 32 clock window in which peripherals are released to implement Flash security, and,
D-FLOP
DQ
C
D-FLOP
D
Q
C
R
56800E
STOP_DIS
Permanent
Disable
Reprogrammable
Disable
Clock
Select
Reset
D
Note: Wait disable circuit is similar
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC56F8147VVFE,MC56F8347VVFE
相关PDF资料
PDF描述
MTFDCAE008SAJ-1M1IT FLOPPY DISK DRIVE CONTROLLER, XMA
MPC8541EVTAJFX 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360
MK1491E-14RLFTR 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
MPC8349ECVVAJF 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672
MK1417SLF 27 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8
相关代理商/技术参数
参数描述
MC56F8347VPYE 功能描述:数字信号处理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
MC56F8347VVF 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
MC56F8347VVFE 功能描述:IC DGTL SIGNAL CTLR 160-MAPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器, 系列:56F8xxx 标准包装:1 系列:87C 核心处理器:MCS 51 芯体尺寸:8-位 速度:16MHz 连通性:SIO 外围设备:- 输入/输出数:32 程序存储器容量:8KB(8K x 8) 程序存储器类型:OTP EEPROM 大小:- RAM 容量:256 x 8 电压 - 电源 (Vcc/Vdd):4 V ~ 6 V 数据转换器:- 振荡器型:外部 工作温度:0°C ~ 70°C 封装/外壳:44-DIP 包装:管件 其它名称:864285
MC56F8355 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-Bit Digital Signal Controllers
MC56F8355MFG60 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Hybrid Controllers