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参数资料
型号： MC56F8347VPY60
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 数字信号处理
英文描述： 16-BIT, 120 MHz, OTHER DSP, PQFP160
封装： PLASTIC, LQFP-160
文件页数： 93/172页
文件大小： 2620K
代理商： MC56F8347VPY60
Signal Pins
56F8347 Technical Data, Rev.11
Freescale Semiconductor
27
Preliminary
TXD1
(GPIOD6)
49
P4
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Transmit Data — SCI1 transmit data output
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
RXD1
(GPIOD7)
50
N5
Input
Input/
Output
Input,
pull-up
enabled
Receive Data — SCI1 receive data input
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
TCK
137
D8
Schmitt
Input
Input,
pulled low
internally
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the
JTAG/EOnCE port. The pin is connected internally to a
pull-down resistor.
TMS
138
A8
Schmitt
Input
Input,
pulled
high
internally
Test Mode Select Input — This input pin is used to
sequence the JTAG TAP controller’s state machine. It is
sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in
the SIM_PUDR register.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
139
B8
Schmitt
Input
Input,
pulled
high
internally
Test Data Input — This input pin provides a serial input data
stream to the JTAG/EOnCE port. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in
the SIM_PUDR register.
TDO
140
D7
Output
In reset,
output is
disabled,
pull-up is
enabled
Test Data Output — This tri-stateable output pin provides a
serial output data stream from the JTAG/EOnCE port. It is
driven in the shift-IR and shift-DR controller states, and
changes on the falling edge of TCK.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC56F8147VVFE,MC56F8347VVFE
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相关代理商/技术参数
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