参数资料
型号: MC56F8347VPYE
厂商: Freescale Semiconductor
文件页数: 101/172页
文件大小: 0K
描述: IC DSP 16BIT 60MHZ 160-LQFP
标准包装: 40
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 60MHz
连通性: CAN,EBI/EMI,SCI,SPI
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 76
程序存储器容量: 136KB(68K x 16)
程序存储器类型: 闪存
RAM 容量: 6K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 16x12b
振荡器型: 外部
工作温度: -40°C ~ 105°C
封装/外壳: 160-LQFP
包装: 托盘
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8347 Technical Data, Rev.11
34
Freescale Semiconductor
Preliminary
ISB0
(GPIOD10)
61
N8
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
ISB0 - 2 — These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMB.
Port D GPIO — These GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to ISB functionality.
To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOD_PUR register. For details, see
ISB1
(GPIOD11)
63
L8
ISB2
(GPIOD12)
64
P8
FAULTB0
67
N9
Schmitt
Input
Input,
pull-up
enabled
FAULTB0 - 3 — These four fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.
To deactivate the internal pull-up resistor, set the PWMB bit
in the SIM_PUDR register. For details, see Part 6.5.8.
FAULTB1
68
L9
FAULTB2
69
L10
FAULTB3
72
P11
ANA0
100
G13
Input
Analog
Input
ANA0 - 3 — Analog inputs to ADC A, channel 0
ANA1
101
H13
ANA2
102
G12
ANA3
103
F13
ANA4
104
F12
Input
Analog
Input
ANA4 - 7 — Analog inputs to ADC A, channel 1
ANA5
105
H14
ANA6
106
G14
ANA7
107
E13
VREFH
113
D14
Input
Analog
Input
VREFH — Analog Reference Voltage High. VREFH must be
less than or equal to VDDA_ADC.
VREFP
112
D13
Input/
Output
Analog
Input/
Output
VREFP, VREFMID & VREFN — Internal pins for voltage
reference which are brought off-chip so they can be
bypassed. Connect to a 0.1
μF low ESR capacitor.
VREFMID
111
E14
VREFN
110
F14
VREFLO
109
E12
Input
Analog
Input
VREFLO — Analog Reference Voltage Low. This should
normally be connected to a low-noise VSS.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
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