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参数资料
型号： MC56F8355VFG60
厂商： MOTOROLA INC
元件分类： 数字信号处理
英文描述： 4-BIT, 120 MHz, OTHER DSP, PQFP128
封装： LQFP-128
文件页数： 17/152页
文件大小： 2224K
代理商： MC56F8355VFG60
Flash Access Blocking Mechanisms
56F8355 Technical Data
113
Preliminary
Proper implementation of Flash security requires that no access to the EOnCE port is provided
when security is enabled. The 56800E core has an input which disables reading of internal memory
via the JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the
FM security bytes.
7.2.3
Flash LOCKOUT_RECOVERY
If a user inadvertently enables security on the 56F8355, a lockout recovery mechanism is provided
which allows the complete erasure of the internal Flash contents, including the configuration field,
and thus disables security (the protection register is cleared). This does not compromise security,
as the entire contents of the user’s secured code stored in Flash are erased before security is
disabled on the 56F8355 on the next reset or power-up sequence. To start the lockout recovery
sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the
chip-level TAP controller’s instruction register.
The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used
to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used
to control the period of the clock used for timed events in the FM erase algorithm. This register
must be set with appropriate values before the lockout sequence can begin. Refer to the JTAG
section of the 56F8300 Peripheral User Manual for more details on setting this register value.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that
divides down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will
map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of
PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The
“Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300
Peripheral User Manual gives specific equations for calculating the correct values.
Figure 7-1 JTAG to FM Connection for LOCKOUT_RECOVERY
Two examples of FM_CLKDIV calculations follow.
JTAG
FMCLKD
DIVIDER
7
FM_CLKDIV
FM_ERASE
Flash Memory
clock
input
SYS_CLK
2
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相关代理商/技术参数
参数描述
MC56F8355VFGE 功能描述:数字信号处理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
MC56F8356 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:56F8356 16-bit Hybrid Controller
MC56F8356MFV60 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC56F8356MFVE 功能描述:数字信号处理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
MC56F8356VFV60 功能描述:数字信号处理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
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